Applied ML – Functional Verification Engineer
San Jose
Workplace: OnsiteFull timeFunction: Software EngineeringExperience: 4+ yearsEducation: bachelorsSkills: ["Communication","Teamwork","Problem-solving","Self-motivated","Continuous learning"]Join Cadence to advance pre-silicon verification by applying machine learning to formal verification and simulation/UVM methods. You’ll work on the ChipStack AI Super Agent initiative, collaborating with ML and software engineers to design, verify, and deploy agentic AI solutions that accelerate ASIC verification, using Verilog, SystemVerilog, Python, and AI-enabled EDA tools to boost productivity up to 10x.
