Cadence Design Systems

3 weeks ago

Lead Application Engineer – Sign-Off

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Lead the adoption of Cadence’s physical design and static verification solutions with key regional customers. Combine deep physical design expertise with technical leadership and customer engagement to help teams achieve optimal performance, power, and area on advanced technology nodes. Perform timing closure, power/signal integrity signoff, and EM/IR signoff, and support next-generation methodology and flow development through to successful tapeouts.

Location: Malaysia

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Sr. Manager level

Key Responsibilities

•Support and drive adoption of Cadence digital implementation, physical design, and static verification solutions with regional customers.
•Perform timing closure, power/signal integrity signoff, and EM/IR signoff for advanced technology node designs.
•Participate in or lead next-generation physical design methodology and flow development.
•Work closely with customer RTL design teams to ensure successful tapeouts.
•Collaborate with Cadence R&D and Product Engineering to influence methodologies and ensure successful project execution and tool adoption.

Key Requirements

•BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
•Experience with ASIC design flow and static timing analysis.
•Strong understanding of EM/IR analysis and power/signal integrity signoff.
•Prior knowledge of timing and IR drop closure in 3DIC technologies is an added advantage.
•Ability to take ownership of technical tasks, work independently, and be hands-on across design verification and characterization.

Experience:3+ yearsASIC design

Education:Bachelor's in EE/CS

Skills:Technical leadershipCustomer engagementIndependent workTeamworkCommunication

Languages:English

Tech Stack:ASIC design flowStatic timing analysisEM/IR analysisPower/signal integrity signoffTiming closureIR drop closure3DICRTLTapeouts

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

3 weeks ago

Lead Application Engineer – Sign-Off

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 7 hours agoStatus: Live

Job Summary

Location: Malaysia

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Sr. Manager level

Key Responsibilities

•Support and drive adoption of Cadence digital implementation, physical design, and static verification solutions with regional customers.
•Perform timing closure, power/signal integrity signoff, and EM/IR signoff for advanced technology node designs.
•Participate in or lead next-generation physical design methodology and flow development.
•Work closely with customer RTL design teams to ensure successful tapeouts.
•Collaborate with Cadence R&D and Product Engineering to influence methodologies and ensure successful project execution and tool adoption.

Key Requirements

•BS/MS in EE/CS with 3+ years of hands-on experience in physical design and verification.
•Experience with ASIC design flow and static timing analysis.
•Strong understanding of EM/IR analysis and power/signal integrity signoff.
•Prior knowledge of timing and IR drop closure in 3DIC technologies is an added advantage.
•Ability to take ownership of technical tasks, work independently, and be hands-on across design verification and characterization.

Experience:3+ yearsASIC design

Education:Bachelor's in EE/CS

Skills:Technical leadershipCustomer engagementIndependent workTeamworkCommunication

Languages:English

Tech Stack:ASIC design flowStatic timing analysisEM/IR analysisPower/signal integrity signoffTiming closureIR drop closure3DICRTLTapeouts

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor