Senior AI Verification Chip Design Engineer

Build and deploy AI-driven pre-silicon verification environments that replace manual testbenches with automated stimulus generation and coverage closure. Develop AI agents and ML models integrated into the verification toolchain to enable intent-to-testbench workflows and intelligent debugging of simulation failures. Apply LLMs and reinforcement learning to reduce state-space explosion, working with design automation teams and EDA vendors from RTL to GDS, and train the team on human-in-the-loop methodologies.