R&D Engineer IC Design 4

Broadcom
Austin
Workplace: OnsiteFull timeUSD 121,900 - 195,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Independent work","Team collaboration","Simulation and debugging","Timing analysis","Analysis"]

Own front-end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and constraint development. Verify designs via simulation and formal verification, and analyze timing from physical implementation. Translate system requirements into logic blocks, simulate and debug with Verilog, and work across the full ASIC implementation flow. Proficiency with RTL synthesis/timing tools, verification tools, DFT/scan, and scripting is required.

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FursaFursa
Broadcom
Broadcom
1 month ago

R&D Engineer IC Design 4

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 25 days agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Own front-end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and constraint development. Verify designs via simulation and formal verification, and analyze timing from physical implementation. Translate system requirements into logic blocks, simulate and debug with Verilog, and work across the full ASIC implementation flow. Proficiency with RTL synthesis/timing tools, verification tools, DFT/scan, and scripting is required.
Location: Austin
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Define architecture and perform front-end design work for ASIC design blocks.
  • •Develop logic, synthesis, and constraints, and implement timing from physical implementation.
  • •Verify designs through simulation and formal verification; analyze timing and debug issues.
  • •Design logic blocks from systems requirements and support the full ASIC design/implementation flow.
  • •Use required tools and scripting to run synthesis, timing analysis, formal verification, linting, power analysis, and DFT/scan activities.

Pay and Benefits

Salary: USD 121,900 - 195,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEquityPaid Leave

Key Requirements

  • •BS/MS in Electrical or Computer Engineering (or equivalent).
  • •Bachelors with 8+ years related experience, or Masters with 6+ years related experience.
  • •Experience with complete ASIC (or standard product) implementation flow from RTL synthesis through timing analysis/closure.
  • •Proficiency with TCL/Perl scripting and synthesis tools (Synopsys Design Compiler/DC topo or Cadence RTL compiler).
  • •Proficiency with timing analysis (Primetime, liberty LIB models) and formal verification tools (Synopsys Formality or Cadence Conformal), plus DFT/scan, lint (Spyglass Lint), power analysis, and version control (svn/git).
Experience:8+ yearsASICSemiconductorsRTLHardware design
Education:Bachelor's in Electrical or Computer Engineering
Skills:Independent workTeam collaborationSimulation and debuggingTiming analysisAnalysis
Tech Stack:VerilogTCLPerlSynopsys Design CompilerDC topoCadence RTL compilerPrimetimeLiberty LIBSynopsys FormalityCadence ConformalSpyglass LintSVNGitRTL synthesisFormal verificationDFTScan methodologyPower analysisTiming analysis

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn