R&D Engineer IC Design 4

Own front-end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and constraint development. Verify designs via simulation and formal verification, and analyze timing from physical implementation. Translate system requirements into logic blocks, simulate and debug with Verilog, and work across the full ASIC implementation flow. Proficiency with RTL synthesis/timing tools, verification tools, DFT/scan, and scripting is required.