Lead Product Validation Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 3-6 yearsEducation: bachelorsSkills: ["Communication","Presentation","Collaboration","Problem-solving","Learning agility"]

Lead product validation engineering focused on functional verification of complex digital systems (SoC) using HDL languages (Verilog/VHDL), SystemVerilog/UVM, and EDA tools. Will design and implement verification environments, automate processes, and leverage scripting to debug verification challenges, contributing to Cadence’s advanced hardware-software IP solutions from Noida, India.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
7 months ago

Lead Product Validation Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 2 years ago

Job Summary

Lead product validation engineering focused on functional verification of complex digital systems (SoC) using HDL languages (Verilog/VHDL), SystemVerilog/UVM, and EDA tools. Will design and implement verification environments, automate processes, and leverage scripting to debug verification challenges, contributing to Cadence’s advanced hardware-software IP solutions from Noida, India.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Sr. Manager level

Key Responsibilities

  • •Verify designs using HDLs and simulate/emulate to validate functional correctness.
  • •Design and implement complex functional verification environments for SoCs.
  • •Debug verification problems using EDA tools and scripting for process automation.
  • •Develop and maintain SystemVerilog/UVM based testbenches and HVL like SystemVerilog.
  • •Collaborate across teams to ensure customer-ready verification results and drive quality.

Key Requirements

  • •B.Tech/B.E./M.E. in Electrical, Electronics or Computer Science with 3-6 years of experience in relevant area.
  • •Strong understanding of HDLs (Verilog and/or VHDL) with prior simulation/emulation experience.
  • •Good working knowledge of EDA tools (Cadence or others) for debugging design/verification problems.
  • •Experience with SystemVerilog, C++, UVM; hardware verification languages (HVL) like SystemVerilog.
  • •Experience in designing and implementing complex functional verification environments; knowledge of PCIe, USB3/4, DP is a plus.
Experience:3-6 yearsHardware verificationSoC verificationEDAVerilogSystemVerilogUVMC++
Education:Bachelor's
Skills:CommunicationPresentationCollaborationProblem-solvingLearning agility
Languages:English
Tech Stack:VerilogVHDLSystemVerilogUVMC++EDA toolsCadenceSoC verificationPCIeUSB3USB4DPScripting

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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