SoC Static Timing Analysis (STA) Engineer, HBM
United States
Workplace: OnsiteFull timeUSD 199,000 - 347,000 annuallyFunction: QA, Test & Release EngineeringExperience: 15+ yearsSkills: ["Collaboration","Communication","Analytical problem-solving","Methodology development","Hands-on execution"]Own chip-level static timing analysis and timing sign-off for next-generation HBM products within the Heterogeneous Integration Group. Partner across RTL design, physical design, architecture, DFT, verification, and product teams to drive timing closure across modes, corners, PVT, and hierarchical constraints. Build Python/Tcl automation and organization methods, lead signal integrity/crosstalk analysis, and perform pre-/post-silicon timing correlation to set standards and readiness gates through tape-out.
Loading
Loading job details...
Preparing the role view and application actions.

