SoC Static Timing Analysis (STA) Engineer, HBM

Micron Technology
United States
Workplace: OnsiteFull timeUSD 199,000 - 347,000 annuallyFunction: QA, Test & Release EngineeringExperience: 15+ yearsSkills: ["Collaboration","Communication","Analytical problem-solving","Methodology development","Hands-on execution"]

Own chip-level static timing analysis and timing sign-off for next-generation HBM products within the Heterogeneous Integration Group. Partner across RTL design, physical design, architecture, DFT, verification, and product teams to drive timing closure across modes, corners, PVT, and hierarchical constraints. Build Python/Tcl automation and organization methods, lead signal integrity/crosstalk analysis, and perform pre-/post-silicon timing correlation to set standards and readiness gates through tape-out.

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Micron Technology
Micron Technology
2 weeks ago

SoC Static Timing Analysis (STA) Engineer, HBM

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Last checked: 2 hours agoStatus: Live

Job Summary

Own chip-level static timing analysis and timing sign-off for next-generation HBM products within the Heterogeneous Integration Group. Partner across RTL design, physical design, architecture, DFT, verification, and product teams to drive timing closure across modes, corners, PVT, and hierarchical constraints. Build Python/Tcl automation and organization methods, lead signal integrity/crosstalk analysis, and perform pre-/post-silicon timing correlation to set standards and readiness gates through tape-out.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Own end-to-end chip-level static timing analysis and timing sign-off across checks, modes, corners, and voltage/temperature conditions.
  • •Develop, maintain, and validate sign-off quality SDC for clocks, resets, HBM interfaces, DFT, and configuration logic.
  • •Drive timing closure from block to full-chip levels using critical path analysis, ECOs, and close collaboration with physical design.
  • •Perform multi-mode/multi-corner analysis including clock domain crossing timing and on-chip variation methodologies.
  • •Build and maintain static timing analysis automation and flows (Python/Tcl), including reporting, regression tracking, dashboards, and post-silicon timing correlation.

Pay and Benefits

Salary: USD 199,000 - 347,000 annually
Perks:Health InsuranceDentalVisionPaid LeavePaid Holidays

Key Requirements

  • •15+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off on multiple tape-outs at 5nm or below.
  • •Deep expertise with static timing analysis tools such as Synopsys PrimeTime and/or Cadence Tempus.
  • •Expert understanding of advanced timing concepts including multi-mode multi-corner analysis, on-chip variation, signal integrity, and power-aware timing.
  • •Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
  • •Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and quality of results reporting.
Experience:15+ yearsSemiconductorsHBMSoCEDA
Skills:CollaborationCommunicationAnalytical problem-solvingMethodology developmentHands-on execution
Tech Stack:Synopsys PrimeTimeCadence TempusPythonTclSDCECOHBMHBM interfacesDFTMMMCOCVAOCVPOCVPython automationTiming correlation

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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