DFT ATPG Design and Test Engineer

AMD
United States
Workplace: HybridFull timeFunction: QA, Test & Release EngineeringEducation: bachelorsSkills: ["Analytical","Detail-oriented","Problem-solving","Ownership","Cross-team communication"]

Own scan test pattern delivery for next-generation CPU cores and caches, from generation and validation through manufacturing readiness. Partner with product test teams to bring up tests and troubleshoot pattern/model/netlist issues. Improve scan architecture and coverage, perform ATPG and gate-level netlist analysis, and collaborate with physical design engineers on design-closure support for static timing, CDC, netlist, and power analysis.

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FursaFursa
AMD
AMD
1 week ago

DFT ATPG Design and Test Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Own scan test pattern delivery for next-generation CPU cores and caches, from generation and validation through manufacturing readiness. Partner with product test teams to bring up tests and troubleshoot pattern/model/netlist issues. Improve scan architecture and coverage, perform ATPG and gate-level netlist analysis, and collaborate with physical design engineers on design-closure support for static timing, CDC, netlist, and power analysis.
Location: United States
Workplace: Hybrid
Employment Type: Full time
Job Function: QA, Test & Release Engineering

Key Responsibilities

  • •Generate, validate, and deliver scan test patterns for next-generation CPU cores and caches.
  • •Partner with product test teams during test bring-up and troubleshoot pattern, model, and netlist issues.
  • •Improve scan architecture, scan coverage, test models, execution methods, and overall product quality.
  • •Perform ATPG pattern and gate-level netlist analysis to identify and resolve testability and coverage issues.
  • •Collaborate with physical design engineers to support design closure through static timing, clock-domain crossing, netlist, and power analysis.

Key Requirements

  • •Experience with design-for-test methodologies, particularly scan test and automatic test pattern generation.
  • •Strong working knowledge of industry-standard ATPG tools for pattern generation, fault coverage, and product quality.
  • •Experience debugging ATPG patterns, scan structures, test models, and gate-level netlists.
  • •Understanding of IEEE 1149.1 boundary scan, IEEE 1500 embedded core test, and memory BIST concepts.
  • •Familiarity with multi-clock and multi-power-domain designs plus static timing analysis, clock-domain crossing, and static power analysis.
Experience:ASIC
Education:Bachelor's in Electrical Engineering or Computer Engineering (or related technical field)
Skills:AnalyticalDetail-orientedProblem-solvingOwnershipCross-team communication
Tech Stack:DFTATPGScan testAutomatic test pattern generationScan architectureFault coverageIEEE 1149.1IEEE 1500Boundary scanEmbedded core testMemory BISTMulti-clockMulti-power-domainStatic timing analysisClock-domain crossingStatic power analysisGate-level netlistsStatic timingCDC analysis

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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