Broadcom

3 months ago

R&D Engineer Adv Tech Dev (PKE) / Sr. Staff

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Senior packaging-focused hardware engineer collaborating with IC design, system design, and packaging teams to select cost-effective, high-performance packages for advanced silicon nodes (5nm, 3nm, 2nm and beyond). Responsible for CPI/SI/PI, thermal requirements, new materials, BOM definition, NPI brings-up, and production ramp with external suppliers and QA.

Location: Singapore

Workplace: Onsite

Employment Type: Full time

Job Function: Research & Scientific (R&D)

Seniority: Sr. Manager level

Key Responsibilities

•Design and select optimum package solutions with BU marketing and IC design teams, ensuring CPI, SI/PI, and thermal requirements are met for advanced silicon products.
•Manage IC packaging activity from concept through development, qualification and high-volume production.
•Define assembly BOM, processes, and troubleshoot packaging issues on new advanced technology.
•Implement and productize newly developed technologies into high-volume manufacturing (HVM) and create package design documentation and assembly instructions.
•Interface with packaging assembly, substrate suppliers, QA, customers, and other operations groups; participate in package technology development and productivity projects.

Key Requirements

•Education: BS/MS/PhD in STEM/Material Science/Electrical/Mechanical Engineering; BS+8 years, MS+6 years, or PhD+3 years experience required.
•Deep understanding of signal integrity and power integrity concepts (characteristic impedance, s-parameters, power plane impedance, optimization).
•Strong authority on Cadence APD for custom substrate design.
•Hands-on expertise with advanced assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (5nm, 3/2nm and beyond).
•Knowledge of materials related to Chip Packaging Interaction (CPI) and wafer BEOL related CPI (top metal, passivation, UBM, bumping).

Experience:SemiconductorPackagingIC packaging

Education:Bachelor's in STEM/Material Science/Electrical/Mechanical Engineering

Skills:Project managementLeadershipCommunicationTroubleshooting

Tech Stack:Cadence APDFlipchipMCM2.5D3DICCPIWafer BEOL

Company Brief

Broadcom

Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Irvine, United States

Founded: 1991

Website LinkedIn

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Broadcom

3 months ago

R&D Engineer Adv Tech Dev (PKE) / Sr. Staff

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 4 hours agoStatus: Live

Job Summary

Location: Singapore

Workplace: Onsite

Employment Type: Full time

Job Function: Research & Scientific (R&D)

Seniority: Sr. Manager level

Key Responsibilities

•Design and select optimum package solutions with BU marketing and IC design teams, ensuring CPI, SI/PI, and thermal requirements are met for advanced silicon products.
•Manage IC packaging activity from concept through development, qualification and high-volume production.
•Define assembly BOM, processes, and troubleshoot packaging issues on new advanced technology.
•Implement and productize newly developed technologies into high-volume manufacturing (HVM) and create package design documentation and assembly instructions.
•Interface with packaging assembly, substrate suppliers, QA, customers, and other operations groups; participate in package technology development and productivity projects.

Key Requirements

•Education: BS/MS/PhD in STEM/Material Science/Electrical/Mechanical Engineering; BS+8 years, MS+6 years, or PhD+3 years experience required.
•Deep understanding of signal integrity and power integrity concepts (characteristic impedance, s-parameters, power plane impedance, optimization).
•Strong authority on Cadence APD for custom substrate design.
•Hands-on expertise with advanced assembly processes for flipchip, MCM packages, and 2.5D for advanced node silicon products (5nm, 3/2nm and beyond).
•Knowledge of materials related to Chip Packaging Interaction (CPI) and wafer BEOL related CPI (top metal, passivation, UBM, bumping).

Experience:SemiconductorPackagingIC packaging

Education:Bachelor's in STEM/Material Science/Electrical/Mechanical Engineering

Skills:Project managementLeadershipCommunicationTroubleshooting

Tech Stack:Cadence APDFlipchipMCM2.5D3DICCPIWafer BEOL

Company Brief

Broadcom

Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Irvine, United States

Founded: 1991

Website LinkedIn