Subsystem/SoC Level Verification Engineer

Own Ethernet subsystem/SoC functional verification, building verification environments with SystemVerilog and UVM. Develop BFMs, checkers, monitors, and scoreboards, create block/system verification plans and tests, and debug failures to root cause. Work with code and functional coverage, perform constrained-random verification, and support gate-level/SDF simulations for Ethernet (MAC, PCS, SerDes) across IP/subsystem/SoC projects using Cadence/Synopsys and scripting (Perl, Tcl).