Cadence Design Systems

6 days ago

Sr Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 hours agoStatus: Live

Job Summary

Drive customer adoption of Cadence Quantus signoff parasitic extraction and Voltus-Fi EMIR solutions through guided pre-sales and post-sales technical engagements. Support customer benchmarks and evaluations to validate accuracy, performance, and value. Deliver technical demos, product presentations, and proof-of-concepts with mentoring, collaborating with sales, account teams, R&D, and field stakeholders to enable successful design wins.

Location: Austin, San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Mid level

Key Responsibilities

•Drive customer adoption of Cadence Quantus signoff parasitic extraction and Voltus-Fi EMIR solutions through guided pre-sales and post-sales technical engagements.
•Support and execute customer benchmarks and evaluations to demonstrate product accuracy, performance, and value under supervision.
•Develop and deliver technical demonstrations, product presentations, and proof-of-concepts with mentoring.
•Collaborate with sales management, account teams, and customers to understand technical requirements and support business opportunities.
•Provide pre-sales technical support in customer meetings, evaluations, and presentations to help drive successful design wins.

Pay and Benefits

Salary: USD 84,000 - 156,000 annually

Equity and Bonus:Equity

Perks:Paid Leave401kEquityHealth InsuranceDentalVision

Key Requirements

•Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
•Coursework or internship experience in VLSI design, physical design, or signoff flows, including exposure to parasitic extraction, EMIR, timing, or physical verification concepts.
•Basic understanding of IC layout, netlists, LVS, and signoff methodologies.
•Familiarity with Linux/UNIX environments and EDA tool workflows.
•Strong analytical and problem-solving skills and good written and verbal communication for customer-facing technical roles.

Experience:EDASemiconductor designVLSIPhysical verification

Education:Master's in Electrical Engineering or Computer Engineering

Skills:Analytical thinkingProblem-solvingCommunicationTeamworkCustomer engagement

Tech Stack:Cadence QuantusVoltus-FiEMIRVirtuosoPegasusSpectreVLSI designPhysical designParasitic extractionIC layoutNetlistsLVSSignoff methodologiesLinux/UNIXEDA tool workflowsTclPythonShell scripting

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

6 days ago

Sr Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 hours agoStatus: Live

Job Summary

Location: Austin, San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Mid level

Key Responsibilities

•Drive customer adoption of Cadence Quantus signoff parasitic extraction and Voltus-Fi EMIR solutions through guided pre-sales and post-sales technical engagements.
•Support and execute customer benchmarks and evaluations to demonstrate product accuracy, performance, and value under supervision.
•Develop and deliver technical demonstrations, product presentations, and proof-of-concepts with mentoring.
•Collaborate with sales management, account teams, and customers to understand technical requirements and support business opportunities.
•Provide pre-sales technical support in customer meetings, evaluations, and presentations to help drive successful design wins.

Pay and Benefits

Salary: USD 84,000 - 156,000 annually

Equity and Bonus:Equity

Perks:Paid Leave401kEquityHealth InsuranceDentalVision

Key Requirements

•Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
•Coursework or internship experience in VLSI design, physical design, or signoff flows, including exposure to parasitic extraction, EMIR, timing, or physical verification concepts.
•Basic understanding of IC layout, netlists, LVS, and signoff methodologies.
•Familiarity with Linux/UNIX environments and EDA tool workflows.
•Strong analytical and problem-solving skills and good written and verbal communication for customer-facing technical roles.

Experience:EDASemiconductor designVLSIPhysical verification

Education:Master's in Electrical Engineering or Computer Engineering

Skills:Analytical thinkingProblem-solvingCommunicationTeamworkCustomer engagement

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor