Digital Verification Engineer - FEC - New Grad

Implement verification strategies for Ciena’s WaveLogic ASICs supporting Forward Error Correction (FEC). You’ll read architecture and functional specs, collaborate with FEC designers and systems teams, and validate functional blocks using simulation, formal, and coverage methods. Build self-checking UVM/SystemVerilog testbenches, develop test and coverage plans, run regressions, debug failures with mentor support, and provide regular status updates.