AI Silicon, Design Verification

Unconventional AI
Palo Alto
Workplace: RemoteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Python","Shell","Bash","Linux","UVM","SystemVerilog","Cadence","Synopsys"]

Senior-level hardware verification engineer responsible for defining and implementing end-to-end verification strategies for IP blocks and full-chip tape-out, building scalable testbenches, and collaborating with digital/analog design and software teams to ensure 100% verification closure and high-quality silicon. Requires UVM/SystemVerilog expertise, extensive testbench experience, and automation scripting.

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FursaFursa
Unconventional AI
Unconventional AI
5 months ago

AI Silicon, Design Verification

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 14 hours agoStatus: Live

Job Summary

Senior-level hardware verification engineer responsible for defining and implementing end-to-end verification strategies for IP blocks and full-chip tape-out, building scalable testbenches, and collaborating with digital/analog design and software teams to ensure 100% verification closure and high-quality silicon. Requires UVM/SystemVerilog expertise, extensive testbench experience, and automation scripting.
Location: Palo Alto
Workplace: Remote
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Define, architect, and implement comprehensive verification plans and environments for IP blocks and full chip from specification to tape-out.
  • •Help build verification infrastructure from ground zero to flexible and nimble environments, able to move quickly and scale for growth.
  • •Take full ownership of the verification lifecycle, including the development and maintenance of scalable testbenches, sophisticated test cases, and robust verification environments.
  • •Deploy industry-standard methodologies (UVM/SystemVerilog) to conduct constrained-random stimulus generation, coverage-driven verification, and assertions.
  • •Collaborate closely with digital and analog design teams, as well as software and systems teams, to define verification requirements, debug complex hardware/software interactions, and ensure design integrity.

Pay and Benefits

Perks:Health Insurance401kPaid Leave

Key Requirements

  • •Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
  • •Minimum of 8 years of hands-on verification experience with UVM and SystemVerilog.
  • •Proven track record developing and maintaining complex verification testbenches and automated test environments.
  • •Scripting experience in Python, Shell, or Bash for automation of verification flows and result analysis.
  • •Strong familiarity with Linux and industry-standard tools from Cadence and Synopsys.
Experience:8+ yearsSemiconductorsHardwareVerificationEDA
Education:Bachelor's
Skills:PythonShellBashLinuxUVMSystemVerilogCadenceSynopsys
Languages:English
Tech Stack:UVMSystemVerilogPythonShellBashLinuxCadenceSynopsys

Company Brief

Unconventional AI
Builds customizable AI copilots and fine-tuned large language model solutions to help teams automate workflows, surface actionable insights, and integrate generative AI into business processes across products and operations.
Industry: AI & Machine Learning
Company Size: Small (11 to 50 employees)
Growth: Early Stage Startup
Funding: Seed
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