Ingénieur Vérification Asic R&D (F/H) (Les Clayes-sous-Bois, FR)

Atos
France
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringSkills: ["Communication","Teamwork"]

Join Atos as an ASIC verification engineer in R&D to contribute to functional verification of complex SoCs/ASICs for high-performance servers. You will work on UVM-based verification environments (SystemVerilog/C++) using constraint-random and coverage-driven tests, collaborating with architecture and logic design teams. Responsible for writing verification specs and test plans, developing environments, and analyzing results to improve coverage.

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Atos
Atos
6 months ago

Ingénieur Vérification Asic R&D (F/H) (Les Clayes-sous-Bois, FR)

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Job Summary

Join Atos as an ASIC verification engineer in R&D to contribute to functional verification of complex SoCs/ASICs for high-performance servers. You will work on UVM-based verification environments (SystemVerilog/C++) using constraint-random and coverage-driven tests, collaborating with architecture and logic design teams. Responsible for writing verification specs and test plans, developing environments, and analyzing results to improve coverage.
Location: France
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Acquire knowledge of ASIC architecture and microarchitecture by studying specifications and interacting with architecture and logic design teams.
  • •Draft verification specifications.
  • •Draft test plans in close collaboration with the logic design team.
  • •Develop verification environments (UVM-SystemVerilog/C++) including drivers, monitors, random tests and coverage models.
  • •Monitor, analyze and debug simulation results to ensure coverage goals are met within deadlines.

Pay and Benefits

Perks:Health InsuranceRemote WorkLearning Budget

Key Requirements

  • •Experience in verification of SoC/ASIC and IP complex projects.
  • •Experience with UVM verification methodology.
  • •Development of verification environments using SystemVerilog/C++ (drivers/monitors, constrained random tests, auto-verification checkers and coverage models).
  • •Ability to debug simulation errors and analyze simulation results to improve coverage.
  • •Strong communication and teamwork skills, with ability to switch between French and English in technical contexts.
Experience:SemiconductorHardwareASIC
Skills:CommunicationTeamwork
Languages:FrenchEnglish
Tech Stack:UVMSystemVerilogC++Constraint-RandomCoverage-DrivenSVA

Company Brief

Atos
Global digital services and consulting firm delivering cloud, cybersecurity, big data, digital workplace, and managed services to enterprise and public sector clients. Provides IT transformation, systems integration, and outsourcing solutions worldwide.
Industry: Consulting
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Bezons, France
Founded: 1997
WebsiteLinkedIn