Customer Engagement Architect

Cadence Design Systems
San Jose
Workplace: OnsiteFull timeUSD 185,500 - 344,500 annuallyFunction: Solutions Engineering & Sales EngineeringExperience: 8+ yearsEducation: mastersSkills: ["Communication","Problem-solving","Customer support"]

Serve as part of the HSV Engagement/Support team, partnering with customers, field AE teams, and R&D to provide technical support for Palladium, Protium, and Virtual Protocol (PDAPP) products. Work on performance tuning, debug customer failures, create test cases, and escalate critical “Customer in Distress” issues. Collaborate with R&D on advanced compiler features, verify fixes/patches, support hardware/software deployment, and contribute to enhancement requests and training materials.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
1 day ago

Customer Engagement Architect

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Serve as part of the HSV Engagement/Support team, partnering with customers, field AE teams, and R&D to provide technical support for Palladium, Protium, and Virtual Protocol (PDAPP) products. Work on performance tuning, debug customer failures, create test cases, and escalate critical “Customer in Distress” issues. Collaborate with R&D on advanced compiler features, verify fixes/patches, support hardware/software deployment, and contribute to enhancement requests and training materials.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Solutions Engineering & Sales Engineering
Seniority: Mid level

Key Responsibilities

  • •Work with customers on performance tuning and performance/debug activities for complex EDA designs.
  • •Handle issues reported by field AEs and customers, including critical account escalations (CID) in coordination with R&D managers.
  • •Debug customer-reported failures by producing test cases to replicate failures and logging issues with HSV R&D teams.
  • •Train customers on deploying advanced compiler features and test R&D fixes/patches.
  • •Develop expertise in hardware and firmware support, participate in internal beta activities for new releases, and update product training materials.
Travel: Low travel

Pay and Benefits

Salary: USD 185,500 - 344,500 annually
Perks:Paid LeavePaid Holidays401kHealth InsuranceDentalVisionEquity

Key Requirements

  • •MS in EE/CE with 8+ years of experience in design and/or verification of complex digital designs, or an applications engineering/technical support role.
  • •Strong knowledge of design debug techniques and logic design, plus verification methodologies for complex EDA environments.
  • •Expertise in HDL (Verilog, SystemVerilog, VHDL), including ability to create test cases to replicate customer issues quickly.
  • •Expertise in Unix/Linux scripting (ksh/bash/csh/perl).
  • •Knowledge of assertions/coverage and low power (CPF/UPF); UVM experience is a plus.
Experience:8+ yearsEDAEmulationCompiler featuresTechnical support
Education:Master's in EE/CE
Skills:CommunicationProblem-solvingCustomer support
Tech Stack:PalladiumProtiumVirtual Protocol (PDAPP)HSVAdvanced compiler featuresVerilogSystemVerilogVHDLUnixLinuxKshBashCshPerlTBAUVMAssertionsCoverageCPFUPF

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor