Staff DFT engineer

AMD
Santa Clara
Workplace: HybridFull timeUSD 145,600 - 249,600 annuallyFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Ownership","Problem-solving","Presentation","Communication","Inter-communication","Self-driven"]

Own ATPG/DFT responsibilities for next-generation AMD high-performance cores within the Cores DFT Team, driving first-pass silicon success. Partner with architecture, IP design, physical design, and product engineering teams to ensure high-quality designs and improve operating efficiency. Execute DFT tool flows, debug low coverage and DRC-related issues, and resolve complex test pattern and simulation failures. Support silicon bring-up and post-silicon debug, including ATE validation of DFT features.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
13 hours ago

Staff DFT engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Own ATPG/DFT responsibilities for next-generation AMD high-performance cores within the Cores DFT Team, driving first-pass silicon success. Partner with architecture, IP design, physical design, and product engineering teams to ensure high-quality designs and improve operating efficiency. Execute DFT tool flows, debug low coverage and DRC-related issues, and resolve complex test pattern and simulation failures. Support silicon bring-up and post-silicon debug, including ATE validation of DFT features.
Location: Santa Clara
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Own ATPG/DFT responsibilities for next-generation AMD high-performance cores.
  • •Work closely with architecture, IP design, physical design, and product engineering teams to achieve first-pass silicon success.
  • •Debug DFT-related issues including low coverage and DRC violation fixes with efficient solutions.
  • •Proficiently debug complex test pattern problems and simulation failures.
  • •Support silicon bring-up activities and participate in post-silicon debug and DFT feature validation on ATE.

Pay and Benefits

Salary: USD 145,600 - 249,600 annually

Key Requirements

  • •Experience with DFT tools and ATPG (Stuck-At, At-Speed, Path-Delay) plus scan compression.
  • •Debug low coverage and DRC violation issues, and develop efficient, effective solutions.
  • •Proficiency in logic design using Verilog.
  • •Comfortable working in a Linux environment and writing/using scripting languages such as Perl and TCL.
  • •Knowledge of DFT industrial standards and practices, including ATPG, JTAG, MBIST, and trade-offs between test quality and test time.
Experience:DFT
Education:Bachelor's in Electrical Engineering/Computer Engineering
Skills:OwnershipProblem-solvingPresentationCommunicationInter-communicationSelf-driven
Languages:En-us
Tech Stack:DFTATPGStuck-AtAt-SpeedPath-DelayScan compressionVerilogLinuxPerlTCLJTAGMBISTLBISTIEEE 1149.1IEEE 1500IEEE 1687Tessent ScanTessent ATPGATESilicon bring-up

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn