Product Engineer II (DDR IP)

Cadence Design Systems
Nanjing, Shanghai
Workplace: OnsiteFull timeFunction: Communications, PR & CommunityExperience: 2+ yearsEducation: bachelorsSkills: ["Communication","Prioritization","Ownership","Collaboration","Clear oral and written communication"]

Join a growing memory IP team to support DDR/LPDDR/HBM/GDDR Memory PHY product integration and deployment. You’ll act as the primary technical interface between customers, Cadence R&D, and System Validation, providing pre-sales engagement and post-sales support. Responsibilities include subsystem application issue analysis, RTL and gate-level simulations, controller/PHY integration and QA testing, timing closure support, customer bringup/production test assistance, and contributing to product documentation—leveraging AI tools to improve deliverables.

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Cadence Design Systems
Cadence Design Systems
1 day ago

Product Engineer II (DDR IP)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 16 hours agoStatus: Live

Job Summary

Join a growing memory IP team to support DDR/LPDDR/HBM/GDDR Memory PHY product integration and deployment. You’ll act as the primary technical interface between customers, Cadence R&D, and System Validation, providing pre-sales engagement and post-sales support. Responsibilities include subsystem application issue analysis, RTL and gate-level simulations, controller/PHY integration and QA testing, timing closure support, customer bringup/production test assistance, and contributing to product documentation—leveraging AI tools to improve deliverables.
Location: Nanjing, Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Support pre-silicon integration, usage, and implementation of memory subsystem products.
  • •Assist internal system integration and QA testing for memory subsystem products (controller + PHY).
  • •Analyze and resolve complex subsystem application/implementation issues, and provide guidance to customers.
  • •Help customers with RTL and gate-level simulations to verify functionality and with timing closure/physical integration aspects.
  • •Support post-silicon bringup and production test activities for customers as needed, and contribute to product documentation/checklists.

Key Requirements

  • •B.S. in Electrical/Computer Engineering (or similar) with at least 2 years of relevant experience, or an M.S. in Electrical/Computer Engineering (or similar).
  • •Experience with memory IPs such as DDR5/4/3, LPDDR5/4/3, HBM3, GDDR6 (or similar).
  • •Verilog RTL design and gate-level verification experience.
  • •Synthesis and static timing analysis experience (physical implementation/verification is a plus).
  • •Familiarity with industry-standard DFT flows and test methodologies.
Experience:2+ yearsMemory IPDDRLPDDRHBMGDDR
Education:Bachelor's in Electrical/Computer Engineering
Skills:CommunicationPrioritizationOwnershipCollaborationClear oral and written communication
Tech Stack:DDR5DDR4DDR3LPDDR5LPDDR4LPDDR3HBM3GDDR6VerilogRTLGate-level verificationSimulationSynthesisStatic timing analysisDFTTiming closure

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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