Design Engineer II

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 2-4 yearsEducation: bachelorsSkills: ["Collaboration","Automation","Methodical problem-solving"]

Drive foundry process technology and PDK enablement by validating, deploying, and maintaining PDK components for advanced semiconductor nodes. Benchmark standard cells, SRAM, and custom circuits for power/performance/area, optimize interconnects, and support physical verification workflows (LVS/DRC/parasitic extraction) with strong Spice model understanding. Build automation scripts and collaborate with DTCO teams to translate advanced device architectures into production-ready processes.

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Cadence Design Systems
Cadence Design Systems
2 days ago

Design Engineer II

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Last checked: 1 hour agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Drive foundry process technology and PDK enablement by validating, deploying, and maintaining PDK components for advanced semiconductor nodes. Benchmark standard cells, SRAM, and custom circuits for power/performance/area, optimize interconnects, and support physical verification workflows (LVS/DRC/parasitic extraction) with strong Spice model understanding. Build automation scripts and collaborate with DTCO teams to translate advanced device architectures into production-ready processes.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Validate, deploy, and maintain foundational PDK components tailored for advanced technology nodes.
  • •Conduct standard cell, SRAM, and custom circuit benchmarking and interconnect optimization to improve power, performance, and area.
  • •Design, develop, and maintain scripts and automated execution flows for PDK enablement/validation and PDK analysis.
  • •Partner with internal DTCO groups to turn advanced device architectures into reality.
  • •Bridge process technology and design by driving next-generation semiconductor technology through path-finding methodologies.

Key Requirements

  • •2–4 years of hands-on semiconductor technology analysis and foundry PDK enablement, including co-optimization of PDK components (LVS, DRC, parasitic extraction, spice models).
  • •Strong foundation in CMOS device physics, including advanced architectures such as GAA, FinFETs, and planar MOSFETs.
  • •Deep knowledge of physical verification and EDA workflows: LVS, DRC, parasitic extraction, and transistor-level Spice models.
  • •Experience designing, developing, and maintaining scripts and automated flows for PDK enablement/validation and PDK analysis.
  • •Proven ability collaborating with core PDK development teams and technology enablement/benchmarking groups (Cadence-based tooling is a plus).
Experience:2-4 yearsSemiconductor technologyFoundryPDK enablementPhysical verificationEDA
Education:Bachelor's in Electronics, Electrical Engineering, VLSI, Microelectronics, Semiconductor Technology, or a related field
Skills:CollaborationAutomationMethodical problem-solving
Tech Stack:PDKDTCOLVSDRCParasitic extractionSpiceScriptsAutomationCadence

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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