AMD

1 day ago

Physical Design Lead

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Last checked: 6 hours agoStatus: Live

Job Summary

Play a key role in AMD’s CT India Physical Design team to enable successful package-aware implementation of advanced chiplet, testchip, and high-performance SoC designs. You’ll serve as the link between Package Engineering and Physical Design teams, driving bump planning, package interface definition, die-to-die connectivity, and package-driven floorplanning constraints from early planning through tapeout. Work across SI/PI and packaging technologies (2.5D/3D, interposers) to support power integrity closure and design convergence.

Location: Bengaluru

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Seniority: Mid level

Key Responsibilities

•Own and drive bump planning activities for chiplet, testchip, and SoC designs in collaboration with Package Engineering teams.
•Define and implement package-aware floorplanning constraints, I/O planning, bump maps, and die interface requirements in the physical design database.
•Collaborate with package teams to understand package architecture, routing layers, power delivery requirements, escape routing limitations, and assembly constraints.
•Develop optimized bump assignments considering signal integrity, power integrity, manufacturability, and cost requirements, and coordinate chip-package co-design for advanced packaging technologies.
•Support IR/EM and power integrity closure, work with SI/PI teams on electrical challenges, and participate in package reviews/signoff through tapeout execution.

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field.
•12+ years of industry experience in Package Design, Chip-Package Co-Design, or related semiconductor implementation domains.
•Strong understanding of semiconductor packaging technologies including Flip-Chip, FCBGA, 2.5D/3D packaging, silicon interposers, and chiplet-based architectures.
•Hands-on experience with bump planning, I/O planning, package interface design, and package-driven floorplanning.
•Proficiency with physical design and verification tools (e.g., Fusion compiler/ICC2/Primetime/Redhawk/PTPX) and scripting languages such as Tcl, Perl, Python, or Shell.

Experience:12+ yearsSemiconductor packagingChiplet-based architectures2.5D packaging3D packaging

Education:Master's in Computer/Electronics/Electrical Engineering

Skills:CommunicationCollaborationProblem-solvingAttention to detail

Languages:En-us

Tech Stack:TclPerlPythonShellFusion compilerICC2PrimetimeRedhawkPTPXRTL to GDSFloorplanningPnRPhysical verification

Company Brief

AMD

Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1969

Glassdoor: 3.9

Website LinkedIn

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AMD