Cadence Design Systems

1 day ago

Lead AE - Verification IP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 11 hours agoStatus: Live

Job Summary

Bridge R&D and top customers by delivering technical expertise for the Verification IP (VIP) portfolio. You support pre-sales activities, accelerate VIP adoption, conduct product demos and customer evaluations, and deploy/integrate VIP in customer environments. Partner with Sales and Marketing on requirements and drive business closure, align PE/R&D teams, mentor junior engineers, and enable customers on VIP AI technology. Travel averages ~10%.

Location: Irvine, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Sales

Seniority: Mid level

Key Responsibilities

•Conduct product demonstrations, manage customer evaluations, and run benchmarks to prove tool value.
•Deploy and integrate VIP into customer environments.
•Partner with Sales and Marketing to understand customer requirements and drive business closure.
•Communicate effectively with customers and PE/R&D teams to align on requirements and deliver solutions.
•Mentor junior engineers and provide technical training to customers to foster excellence and adoption.

Travel: Low travel

Pay and Benefits

Salary: USD 102,900 - 191,100 annually

Perks:Paid LeavePaid Holidays401kEquityHealth InsuranceDentalVision

Key Requirements

•2+ years of industry design verification experience.
•Knowledge of AMBA, PCIe, CXL, UCIe, UALink, and UEC protocols.
•Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
•Strong programming skills in Verilog, SystemVerilog, and UVM.
•Ability to debug pre-silicon verification failures using waveform viewers and simulation analysis tools.

Experience:2+ yearsDesign verificationElectronic design

Education:Bachelor's in Electrical Engineering, Computer Engineering

Skills:CommunicationIndependent executionTeam collaborationProblem solvingContinuous learning

Tech Stack:VerilogSystem VerilogUVMAMBAPCIeCXLUCIeUALinkUECWaveform viewersSimulation analysis tools

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cadence Design Systems

1 day ago

Lead AE - Verification IP

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 11 hours agoStatus: Live

Job Summary

Location: Irvine, Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Sales

Seniority: Mid level

Key Responsibilities

•Conduct product demonstrations, manage customer evaluations, and run benchmarks to prove tool value.
•Deploy and integrate VIP into customer environments.
•Partner with Sales and Marketing to understand customer requirements and drive business closure.
•Communicate effectively with customers and PE/R&D teams to align on requirements and deliver solutions.
•Mentor junior engineers and provide technical training to customers to foster excellence and adoption.

Travel: Low travel

Pay and Benefits

Salary: USD 102,900 - 191,100 annually

Perks:Paid LeavePaid Holidays401kEquityHealth InsuranceDentalVision

Key Requirements

•2+ years of industry design verification experience.
•Knowledge of AMBA, PCIe, CXL, UCIe, UALink, and UEC protocols.
•Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
•Strong programming skills in Verilog, SystemVerilog, and UVM.
•Ability to debug pre-silicon verification failures using waveform viewers and simulation analysis tools.

Experience:2+ yearsDesign verificationElectronic design

Education:Bachelor's in Electrical Engineering, Computer Engineering

Skills:CommunicationIndependent executionTeam collaborationProblem solvingContinuous learning

Tech Stack:VerilogSystem VerilogUVMAMBAPCIeCXLUCIeUALinkUECWaveform viewersSimulation analysis tools

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor