Staff Design Verification Engineer

AMD
Singapore
Workplace: HybridFull timeSGD 90,300 - 129,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Presentation","Collaboration","Mentoring","Knowledge sharing"]

Drive verification for DDR5, LPDDR5, and DFI server memory interfaces, partnering with cross-functional teams to align firmware, BIOS, and software with hardware behavior. Develop SystemVerilog/UVM testbenches, coverage models, VIPs/BFMs, and support debug through bring-up and Post-Si issue resolution. Share verification methodology knowledge while engaging in RTL and micro-architecture discussions to plan and execute validation.

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FursaFursa
AMD
AMD
5 days ago

Staff Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Drive verification for DDR5, LPDDR5, and DFI server memory interfaces, partnering with cross-functional teams to align firmware, BIOS, and software with hardware behavior. Develop SystemVerilog/UVM testbenches, coverage models, VIPs/BFMs, and support debug through bring-up and Post-Si issue resolution. Share verification methodology knowledge while engaging in RTL and micro-architecture discussions to plan and execute validation.
Location: Singapore
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive verification efforts for DDR interfaces (DDR5, LPDDR5/LPDDR6, DFI) across DIMMs in server products.
  • •Develop and execute verification plans with a team of verification engineers for DDR5/LPDDR5/DFI memory systems.
  • •Ensure FW, BIOS, and SW are aligned with PHY/system behavior, including HW (silicon) and integration across layers.
  • •Support RTL and micro-architecture discussions for planning and debug with IP/domain architects and design engineers.
  • •Support Post-Si teams for product performance, power, and functional issue debug and resolution; contribute to verification methodology knowledge sharing.

Pay and Benefits

Salary: SGD 90,300 - 129,000 annually

Key Requirements

  • •Advanced knowledge of SystemVerilog and UVM-based verification, including DDR5 and LPDDR5 testbenches and coverage models.
  • •Experience building and implementing verification environments (simulation environments, functional coverage) for DDR5/LPDDR5 systems.
  • •Proficiency with SystemVerilog assertions, constraints, and coverage, with experience in formal verification methods and tool usage beyond standard applications.
  • •Ability to collaborate with hardware, firmware, and software teams to align system-level memory architecture and define validation requirements early.
  • •Bachelor’s or Master’s degree in a related discipline.
Education:Bachelor's in related discipline
Skills:CommunicationPresentationCollaborationMentoringKnowledge sharing
Tech Stack:SystemVerilogUVMCC++PythonPerlRTLDDR5LPDDR5LPDDR6DFIMicro-architecture

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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