Cadence Design Systems

2 days ago

Lead Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Provide technical support for digital IC design implementation, including product demonstrations and sales presentations. Hands-on ownership of the full APR flow (floorplan, placement, timing analysis, CTS, signoff timing, and PV closure), while supporting key customer engagements. Contribute advanced-node tape-out experience where applicable, collaborate with team members with minimal routine guidance, and communicate confidently with customers and stakeholders.

Location: Taiwan

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Mid level

Key Responsibilities

•Deliver key technical support in digital IC design implementation, including product demonstrations and sales presentations.
•Execute the full APR flow end-to-end, covering floorplan, placement, timing analysis, CTS, signoff timing, and PV closure methodology.
•Support customer engagements to help drive business growth.
•Contribute tape-out experience, especially for advanced node designs.
•Take a leading role within the team while receiving limited instruction on routine and general assignments.

Key Requirements

•Master’s degree with 3+ years of experience or Bachelor’s degree with 5+ years in IC design (Cadence Innovus experience is a plus).
•Experience with full APR flow, including logical and physical topics such as timing, SI, congestion, routing DRC, and hierarchical design.
•Knowledge of MSV methodology.
•Be proficient in English and Chinese with good confidence, attitude, and self-motivation.
•Be familiar with shell, Perl, Tcl, or similar scripting languages.

Experience:3+ yearsIC designDigital IC designAdvanced-node design

Education:Master's

Skills:CommunicationSelf-motivationCustomer engagementHands-on technical execution

Languages:EnglishChinese

Tech Stack:APR flowFloorplanPlacementTiming analysisCTSSignoff timingPV closureInnovusSICongestionRouting DRCHier designMSVShellPerlTcl

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

2 days ago

Lead Application Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 23 hours agoStatus: Live

Job Summary

Location: Taiwan

Workplace: Onsite

Employment Type: Full time

Job Function: Administration & Executive Assistance

Seniority: Mid level

Key Responsibilities

•Deliver key technical support in digital IC design implementation, including product demonstrations and sales presentations.
•Execute the full APR flow end-to-end, covering floorplan, placement, timing analysis, CTS, signoff timing, and PV closure methodology.
•Support customer engagements to help drive business growth.
•Contribute tape-out experience, especially for advanced node designs.
•Take a leading role within the team while receiving limited instruction on routine and general assignments.

Key Requirements

•Master’s degree with 3+ years of experience or Bachelor’s degree with 5+ years in IC design (Cadence Innovus experience is a plus).
•Experience with full APR flow, including logical and physical topics such as timing, SI, congestion, routing DRC, and hierarchical design.
•Knowledge of MSV methodology.
•Be proficient in English and Chinese with good confidence, attitude, and self-motivation.
•Be familiar with shell, Perl, Tcl, or similar scripting languages.

Experience:3+ yearsIC designDigital IC designAdvanced-node design

Education:Master's

Skills:CommunicationSelf-motivationCustomer engagementHands-on technical execution

Languages:EnglishChinese

Tech Stack:APR flowFloorplanPlacementTiming analysisCTSSignoff timingPV closureInnovusSICongestionRouting DRCHier designMSVShellPerlTcl

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor