Senior ASIC Timing Engineer, DFT

NVIDIA
United States
Workplace: OnsiteFull timeUSD 136,000 - 218,500 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Analytical thinking","Workflow improvement","Collaboration","Problem-solving","Attention to detail"]

Drive timing analysis and closure for DFT logic across NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs), working at block, cluster, and full-chip levels. Partner with PD, DFX, and clock teams to define timing closure strategy, create timing constraints for custom DFT designs, and implement ECOs to converge timing and power. Improve workflows through automation, resilience, and standardization while building expertise in STA and industry timing convergence tools.

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FursaFursa
NVIDIA
NVIDIA
1 month ago

Senior ASIC Timing Engineer, DFT

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Drive timing analysis and closure for DFT logic across NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs), working at block, cluster, and full-chip levels. Partner with PD, DFX, and clock teams to define timing closure strategy, create timing constraints for custom DFT designs, and implement ECOs to converge timing and power. Improve workflows through automation, resilience, and standardization while building expertise in STA and industry timing convergence tools.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Drive timing analysis and closure for DFT logic on NVIDIA chips across hierarchical levels (block, cluster, full-chip).
  • •Coordinate with PD, DFX, and clock teams to develop timing closure strategy, timing constraints, and implement timing/power convergence ECOs.
  • •Continuously improve workflows and designs by introducing automation, resilience, and standardization.

Pay and Benefits

Salary: USD 136,000 - 218,500 annually
Perks:Equity

Key Requirements

  • •BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience, or MS (or equivalent experience) with 2+ years’ experience.
  • •Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
  • •Expertise analyzing and fixing timing paths through ECOs.
  • •Expertise developing timing constraints.
  • •In-depth knowledge of industry-standard timing convergence tools.
Experience:5+ yearsASICDFTSemiconductor
Education:Bachelor's in Electrical or Computer Engineering
Skills:Analytical thinkingWorkflow improvementCollaborationProblem-solvingAttention to detail
Tech Stack:DFTStatic Timing Analysis (STA)ECOsIJTAGScanTiming constraintsTiming convergence toolsTiming analysis

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
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