Senior ASIC Timing Engineer, DFT

Drive timing analysis and closure for DFT logic across NVIDIA chips (GPUs/CPUs/DPUs/LPUs/SoCs), working at block, cluster, and full-chip levels. Partner with PD, DFX, and clock teams to define timing closure strategy, create timing constraints for custom DFT designs, and implement ECOs to converge timing and power. Improve workflows through automation, resilience, and standardization while building expertise in STA and industry timing convergence tools.