Sr. EDA Tools Engineer - PERC ESD

Intel
United States
Workplace: OnsiteFull timeUSD 149,600 - 284,580 annuallyFunction: QA, Test & Release EngineeringExperience: 3+ yearsEducation: mastersSkills: ["Analytical","Problem-solving","Attention to detail","Organization","Communication"]

Develop and maintain ESD/LU PERC rule decks and reliability design methodologies aligned to Intel’s ESD Design Rule Manual. Build and execute rule debugging, validation, and signoff test cases, define QA requirements, and drive automation for robust, efficient rule checks. Collaborate with internal teams and external EDA vendors to implement tool features, and lead innovation to improve ESD/LU verification automation and solve cross-domain design issues.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Intel
Intel
2 months ago

Sr. EDA Tools Engineer - PERC ESD

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Develop and maintain ESD/LU PERC rule decks and reliability design methodologies aligned to Intel’s ESD Design Rule Manual. Build and execute rule debugging, validation, and signoff test cases, define QA requirements, and drive automation for robust, efficient rule checks. Collaborate with internal teams and external EDA vendors to implement tool features, and lead innovation to improve ESD/LU verification automation and solve cross-domain design issues.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Develop ESD/LU rule decks aligned with the ESD Design Rule Manual and reliability requirements.
  • •Create and maintain reliability ESD and LU design rule methodologies and specifications.
  • •Collaborate with internal design, reliability, and CAD teams and external EDA vendors to define and implement new tool features and requirements.
  • •Build and execute test cases for rule debugging, validation, and signoff.
  • •Define QA requirements and drive automation to improve robustness and efficiency of rule checks.

Pay and Benefits

Salary: USD 149,600 - 284,580 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Master’s degree or PhD in Electrical Engineering or Computer Engineering.
  • •3+ years of experience in physical design verification (reliability, device physics, process technology, design rules, extraction, or related domains).
  • •2+ years of experience with ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools).
  • •2+ years of experience in scripting (e.g., Python, Tcl, Perl or similar) for QA and flow automation.
  • •Strong analytical and problem-solving abilities with excellent attention to detail and organization skills.
Experience:3+ years
Education:Master's in Electrical Engineering or Computer Engineering
Skills:AnalyticalProblem-solvingAttention to detailOrganizationCommunication
Tech Stack:PythonTclPerlESDLUPERCPreSiHBMCDMDRMDRCRunset

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
WebsiteLinkedInGlassdoor