Principal Product Engineer - DIP

Cadence Design Systems
Shanghai
Full timeFunction: Communications, PR & CommunityExperience: 8+ yearsEducation: bachelorsSkills: ["Debugging","Communication","Presentation","Proactive","Collaboration","Strategic thinking"]

Serve as the primary technical interface for complex subsystem application and implementation issues, managing cases through systems like Salesforce and Jira. Support pre- and post-silicon integration and verification of PHY and controller SoC components using RTL and gate-level simulations, including timing closure. Engage customers to triage, prioritize, and escalate critical technical problems, while creating knowledge bases, delivering technical training, and feeding product and R&D improvements. Requires 8+ years in IP verification/design and strong digital electronics expertise.

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Cadence Design Systems
Cadence Design Systems
4 days ago

Principal Product Engineer - DIP

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Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live

Job Summary

Serve as the primary technical interface for complex subsystem application and implementation issues, managing cases through systems like Salesforce and Jira. Support pre- and post-silicon integration and verification of PHY and controller SoC components using RTL and gate-level simulations, including timing closure. Engage customers to triage, prioritize, and escalate critical technical problems, while creating knowledge bases, delivering technical training, and feeding product and R&D improvements. Requires 8+ years in IP verification/design and strong digital electronics expertise.
Location: Shanghai
Employment Type: Full time
Job Function: Communications, PR & Community
Seniority: Mid level

Key Responsibilities

  • •Act as the primary interface for technical issues, driving resolution for complex subsystem application or implementation problems through case management.
  • •Monitor and manage case management systems such as Salesforce (SFDC) and Jira.
  • •Support Pre-Silicon integration, post-silicon bring-up, and verification of PHY and controller SoC integration, including RTL and gate-level simulations and timing closure.
  • •Proactively engage with customers to identify potential issues, prioritize critical technical problems, and manage escalations.
  • •Develop knowledge bases and documentation, deliver technical training/seminars, and provide feedback to internal Product Engineering and R&D teams.

Key Requirements

  • •8+ years of experience in verification and design focused on IP development.
  • •Strong digital electronics expertise with Verilog/SystemVerilog and UVM methodology.
  • •Practical knowledge of memory or communication interface IP protocols (e.g., MIPI, PCI Express, DDR/LPDDR/HBM, USB).
  • •Excellent debugging skills and ability to handle complex problems.
  • •Bachelor’s or Master’s in Electronics or Electrical Engineering.
Experience:8+ years
Education:Bachelor's in Electronics or Electrical Engineering
Skills:DebuggingCommunicationPresentationProactiveCollaborationStrategic thinking
Languages:English
Tech Stack:Salesforce (SFDC)JiraVerilogSystemVerilogUVMRTL simulationGate-level simulationsTCLPerlPythonMIPI (CSI2/DSI/I3C/PHY)PCI ExpressDDRLPDDRHBMUSB

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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