ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years

Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 12+ yearsSkills: ["Verilog","SystemVerilog","VCS","Spyglass","CDC","Formal verification","RTL","ASIC","Verification"]

Senior ASIC engineering leader focused on RTL development and formal verification. Lead RTL design and verification efforts using Verilog/SystemVerilog, VCS, Spyglass, and CDC for complex RTL blocks. Drive verification strategy, mentor engineers, and collaborate with cross-functional teams to deliver high-quality silicon on aggressive schedules.

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FursaFursa
Cisco
Cisco
2 months ago

ASIC Engineering Technical Leader | RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) | Exp - 12+ years

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Job Summary

Senior ASIC engineering leader focused on RTL development and formal verification. Lead RTL design and verification efforts using Verilog/SystemVerilog, VCS, Spyglass, and CDC for complex RTL blocks. Drive verification strategy, mentor engineers, and collaborate with cross-functional teams to deliver high-quality silicon on aggressive schedules.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Provide technical leadership for RTL development and verification of ASIC blocks, defining standards and best practices.
  • •Mentor and guide a team of engineers, review design and verification plans, and drive timely delivery of silicon milestones.
  • •Collaborate with pre- and post-silicon teams to ensure RTL correctness, coverage adequacy, and debugging efficiency.
  • •Champion formal verification approaches and ensure robust CDC checks across blocks to meet reliability targets.
  • •Communicate progress, risks, and mitigations to senior leadership and cross-functional stakeholders.

Key Requirements

  • •12+ years of hands-on ASIC RTL experience with Verilog/SystemVerilog
  • •Proven leadership experience as a technical leader or lead engineer
  • •Strong expertise with VCS, Spyglass, CDC, and Formal Verification methodologies
  • •Experience delivering complex RTL designs and verifying them end-to-end
  • •Excellent collaboration and communication skills to work with cross-functional teams
Experience:12+ yearsSemiconductorHardware
Skills:VerilogSystemVerilogVCSSpyglassCDCFormal verificationRTLASICVerification
Tech Stack:VerilogSystemVerilogVCSSpyglassCDCFormal verificationRTLASIC

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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Glassdoor: 4.0
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