Physical Design PnR Tile Lead

AMD
Markham
Workplace: OnsiteFull timeCAD 135,800 - 232,800 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Technical leadership","Problem-solving","Communication","Mentorship","Execution management"]

Lead physical implementation for complex SoC designs at advanced process nodes, driving Tile Place & Route strategy from floorplan through tapeout. Own execution planning, milestones, risk management, and quality metrics across tiles and critical IPs, coordinating with Architecture, RTL, Timing, CAD, Methodology, Physical Verification, and Full Chip teams. Mentor Tile PnR engineers, conduct technical reviews and root-cause analysis, and help advance implementation methodologies, automation, and AI-enabled design solutions.

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FursaFursa
AMD
AMD
1 day ago

Physical Design PnR Tile Lead

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Job Summary

Lead physical implementation for complex SoC designs at advanced process nodes, driving Tile Place & Route strategy from floorplan through tapeout. Own execution planning, milestones, risk management, and quality metrics across tiles and critical IPs, coordinating with Architecture, RTL, Timing, CAD, Methodology, Physical Verification, and Full Chip teams. Mentor Tile PnR engineers, conduct technical reviews and root-cause analysis, and help advance implementation methodologies, automation, and AI-enabled design solutions.
Location: Markham
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Drive physical implementation of complex SoC tiles from floorplanning through tapeout.
  • •Own Tile PnR strategy including floorplanning, placement, CTS, routing, timing closure, congestion management, IR/EM closure, and signoff readiness.
  • •Plan and manage execution milestones, risks, and quality metrics for critical IPs and SoC tiles; coordinate across multiple design and verification teams.
  • •Lead root-cause analysis and resolution of complex implementation challenges; drive closure on schedule- and tapeout-critical issues.
  • •Mentor Tile PnR engineers, run technical reviews, and lead training and knowledge-sharing while driving adoption of new methodologies and automation.

Pay and Benefits

Salary: CAD 135,800 - 232,800 annually

Key Requirements

  • •BS/MS in Electrical Engineering, Computer Engineering, or a related field.
  • •Industry experience in physical design with multiple successful tape-outs at advanced technology nodes.
  • •Demonstrated technical leadership across multiple projects or product families, including leading critical tiles or IPs.
  • •Recognized expertise in Tile PnR and physical implementation, including congestion analysis, timing, power optimization, and PPA improvement.
  • •Experience with AI-assisted implementation methodologies and familiarity with implementation flows such as ICC2, Innovus, Fusion Compiler, PrimeTime, RedHawk/Totem, and Calibre.
Education:Bachelor's in Electrical Engineering or Computer Engineering
Skills:Technical leadershipProblem-solvingCommunicationMentorshipExecution management
Languages:En-us
Tech Stack:ICC2InnovousFusion CompilerPrimeTimeRedHawk/TotemCalibreI-REMAI-enabled designTile Place & Route (PnR)

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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