Cadence Design Systems

1 month ago

Principal Design Engineer(Virtual Solution)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Lead design and verification for AVIP-based emulation/prototyping platforms, delivering scalable multi-protocol verification across clock domains. Architect end-to-end verification flows and develop custom test assets, collaborating with global teams to bring up Palladium/Protium solutions. Drive AI/ML integration in verification workflows and support customers with deployment and debugging.

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design and develop system-level AVIP solutions for emulation/prototyping platforms.
•Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation.
•Develop end-to-end verification flows including AVIP integration, testbench, and bare-metal/driver-level validation.
•Architect scalable solutions for multi-protocol system validation across multiple clock domains.
•Optimize solutions for performance, scalability, and emulation efficiency.

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5-10 years’ experience.
•Strong RTL design experience (SystemVerilog/Verilog) and C/C++ development for modeling, testbench, or system integration.
•Expertise in high-speed protocols such as PCIe, CXL, AMBA, UCIe, or Ethernet.
•Solid understanding of system-level verification methodologies and emulation/acceleration flows.
•Hands-on experience with Palladium/Protium or FPGA-based emulation (preferred).

Experience:5-10 yearsHigh-speed protocolsRTL designEmulation

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solvingAdaptabilityLearning

Languages:English

Tech Stack:SystemVerilogVerilogC/C++PCIeCXLAMBAUCIeEthernetPalladiumProtiumFPGAEmulationUVMPythonQemuGem5AI/ML

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

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Cadence Design Systems

1 month ago

Principal Design Engineer(Virtual Solution)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Shanghai

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design and develop system-level AVIP solutions for emulation/prototyping platforms.
•Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation.
•Develop end-to-end verification flows including AVIP integration, testbench, and bare-metal/driver-level validation.
•Architect scalable solutions for multi-protocol system validation across multiple clock domains.
•Optimize solutions for performance, scalability, and emulation efficiency.

Key Requirements

•Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5-10 years’ experience.
•Strong RTL design experience (SystemVerilog/Verilog) and C/C++ development for modeling, testbench, or system integration.
•Expertise in high-speed protocols such as PCIe, CXL, AMBA, UCIe, or Ethernet.
•Solid understanding of system-level verification methodologies and emulation/acceleration flows.
•Hands-on experience with Palladium/Protium or FPGA-based emulation (preferred).

Experience:5-10 yearsHigh-speed protocolsRTL designEmulation

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solvingAdaptabilityLearning

Languages:English

Tech Stack:SystemVerilogVerilogC/C++PCIeCXLAMBAUCIeEthernetPalladiumProtiumFPGAEmulationUVMPythonQemuGem5AI/ML

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor