ASIC Design Engineer - New College Grad 2026

NVIDIA
Santa Clara
Workplace: OnsiteFull timeUSD 100,000 - 189,750 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Interpersonal skills","Mentoring"]

Join the CPU Logic Design Team to craft and deliver a specific unit for CPU on-chip interconnect, coherency, and last-level cache. You’ll write readable high-performance, low-power RTL, perform synthesis and timing closure, and document design work. Collaborate with verification and implementation teams to validate correctness and achieve timing, area, performance, and power goals, including supporting super-unit timing closure and lab bring-up/debug.

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FursaFursa
NVIDIA
NVIDIA
1 month ago

ASIC Design Engineer - New College Grad 2026

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Join the CPU Logic Design Team to craft and deliver a specific unit for CPU on-chip interconnect, coherency, and last-level cache. You’ll write readable high-performance, low-power RTL, perform synthesis and timing closure, and document design work. Collaborate with verification and implementation teams to validate correctness and achieve timing, area, performance, and power goals, including supporting super-unit timing closure and lab bring-up/debug.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Entry level

Key Responsibilities

  • •Own and deliver a specific unit on the chip as part of the core CPU team.
  • •Write readable high-performance and low-power RTL, and create design documentation.
  • •Perform synthesis and timing closure for assigned logic.
  • •Collaborate with verification to validate correctness of your unit.
  • •Work with implementation to meet timing, area, performance, and power goals, including assisting super-unit timing closure.

Pay and Benefits

Salary: USD 100,000 - 189,750 annually
Equity and Bonus:Equity

Key Requirements

  • •Recent graduate with a BS or MS in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent experience).
  • •Experience in processor or other high-performance semiconductor designs.
  • •Verilog expertise and a deep understanding of ASIC design flow, including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, and bring-up & lab debug.
  • •Strong computer architecture knowledge, including cache coherency or high-speed interconnects.
  • •Effective communication and interpersonal skills; mentoring junior engineers and interns is a plus.
Experience:SemiconductorProcessor design
Education:Bachelor's in Electrical Engineering, Computer Engineering, or Computer Science
Skills:CommunicationInterpersonal skillsMentoring
Tech Stack:VerilogRTLASICLogic synthesisDFTTiming analysisFloor-planningECOPrototyping

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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