ASIC Design Engineer - New College Grad 2026

Join the CPU Logic Design Team to craft and deliver a specific unit for CPU on-chip interconnect, coherency, and last-level cache. You’ll write readable high-performance, low-power RTL, perform synthesis and timing closure, and document design work. Collaborate with verification and implementation teams to validate correctness and achieve timing, area, performance, and power goals, including supporting super-unit timing closure and lab bring-up/debug.