Senior Digital ASIC Design Engineer
Ciena
Ottawa
Workplace: OnsiteFull timeCAD 109,000 - 174,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","Python","C","C++","SystemC"]Lead design and integration of next-generation ASIC technologies for WaveLogic optical networking, delivering scalable silicon through cross-functional collaboration. Own top-level RTL, libraries, and tool flows; translate architecture into verified designs with systems engineers; validate prototypes in lab environments. Balance independent execution with teamwork in a fast-paced, technology-forward environment at Ciena in Ottawa.
