Cisco

3 weeks ago

ASIC Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 hours agoStatus: Live

Job Summary

Serve as a technical expert for advanced semiconductor packaging technologies, focusing on 2.5D/3D integration with RDL CoW processes and large-body package design. You’ll partner with assembly, substrate, and OSAT suppliers to develop new processes, define integration flows for heterogeneous multiple-die solutions, and create plans for assembly reliability and technology qualification. Drive DfM/DfR solutions with internal teams to address warpage, stress, and SI/PI optimization challenges.

Location: Taipei

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Act as a technical expert to develop and enable advanced packaging processes, modules, and materials across package design, assembly, integration, and substrate manufacturing.
•Engage with assembly suppliers to understand assembly process requirements and module design rules.
•Define assembly process integration and flow for advanced multiple-die heterogeneous integration.
•Develop assembly and reliability plans to evaluate and qualify new package technologies.
•Collaborate with substrate suppliers and internal teams to address design challenges and optimize warpage, stress, SI/PI performance, and board-mount process using DfM/DfR principles.

Key Requirements

•BS/MS/PhD in Mechanical Engineering, Materials Science, Physics, or a closely related field with 5+ years of progressive experience in Semiconductor Packaging and Assembly, leading technical projects or initiatives.
•Proven experience developing and executing advanced packaging technologies such as 2.5D/3D process integration, heterogeneous integration, wafer-level packaging, and package technology qualification.
•Strong knowledge of advanced CoWoS package assembly and manufacturing flow.
•Experience with substrate manufacturing processes, design rules, and material for high-layer-count substrate stack-ups, including multi-layer core technology and impacts to device-level power and signal integrity.
•Experience optimizing package design attributes, material selection, and assembly processes for package warpage, stress, and thermal performance.

Experience:5+ yearsSemiconductor packagingSemiconductor assembly

Education:

Skills:Problem-solvingCommunicationPresentationInfluencingData analysis

Tech Stack:2.5D3DRDL CoWHeterogeneous integrationWafer-level packagingCoWoSSI/PIDfMDfR8DFMEAStatistical process controlCADCadenceSolidWorksAutoCAD

Company Brief

Cisco

Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cisco

3 weeks ago

ASIC Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 9 hours agoStatus: Live

Job Summary

Location: Taipei

Workplace: Hybrid

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Mid level

Key Responsibilities

•Act as a technical expert to develop and enable advanced packaging processes, modules, and materials across package design, assembly, integration, and substrate manufacturing.
•Engage with assembly suppliers to understand assembly process requirements and module design rules.
•Define assembly process integration and flow for advanced multiple-die heterogeneous integration.
•Develop assembly and reliability plans to evaluate and qualify new package technologies.
•Collaborate with substrate suppliers and internal teams to address design challenges and optimize warpage, stress, SI/PI performance, and board-mount process using DfM/DfR principles.

Key Requirements

•BS/MS/PhD in Mechanical Engineering, Materials Science, Physics, or a closely related field with 5+ years of progressive experience in Semiconductor Packaging and Assembly, leading technical projects or initiatives.
•Proven experience developing and executing advanced packaging technologies such as 2.5D/3D process integration, heterogeneous integration, wafer-level packaging, and package technology qualification.
•Strong knowledge of advanced CoWoS package assembly and manufacturing flow.
•Experience with substrate manufacturing processes, design rules, and material for high-layer-count substrate stack-ups, including multi-layer core technology and impacts to device-level power and signal integrity.
•Experience optimizing package design attributes, material selection, and assembly processes for package warpage, stress, and thermal performance.

Experience:5+ yearsSemiconductor packagingSemiconductor assembly

Education:

Skills:Problem-solvingCommunicationPresentationInfluencingData analysis

Tech Stack:2.5D3DRDL CoWHeterogeneous integrationWafer-level packagingCoWoSSI/PIDfMDfR8DFMEAStatistical process controlCADCadenceSolidWorksAutoCAD

Company Brief

Cisco

Industry: Networking Equipment

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1984

Glassdoor: 4.0

Website LinkedIn Glassdoor