Sr Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Leadership","Communication","Problem-solving","Teamwork"]

Lead design verification initiatives for complex electrical/VLSI designs, guiding projects from concept to verification closure. Own UVM/SystemVerilog based verification environments, develop test plans, and ensure robust functional verification fundamentals. Requires 12+ years of DV experience, strong hands-on coding, and memory IP verification exposure.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 12 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Lead design verification initiatives for complex electrical/VLSI designs, guiding projects from concept to verification closure. Own UVM/SystemVerilog based verification environments, develop test plans, and ensure robust functional verification fundamentals. Requires 12+ years of DV experience, strong hands-on coding, and memory IP verification exposure.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead design verification projects from concept to verification closure.
  • •Develop and maintain functional verification environments (UVM/SystemVerilog) for complex designs.
  • •Create and execute test plans, environment development, and verification strategies.
  • •Verify complex designs and IPs, with focus on memory IP (DDR/HBM/GDDR) verification familiarity.
  • •Collaborate with cross-functional teams to ensure verification coverage and quality.

Key Requirements

  • •BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer
  • •12+ years of Design Verification experience with SV/UVM
  • •Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • •Design Verification experience verifying complex designs and leading projects from concept to verification closure
  • •Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required
Experience:12+ yearsSemiconductorEDAVLSI
Education:Bachelor's in Electrical / Electronics / VLSI
Skills:LeadershipCommunicationProblem-solvingTeamwork
Tech Stack:SystemVerilogUVMVerilogSVTestingVerification environments

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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