3 months ago

Senior ASIC DV Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Verifies complex SOCs for Touch Controllers and Wireless Charging, architecting block and full-chip verification environments and validating RTL, mixed-signal interfaces, UPF low-power flows, and bug fixes across simulation, FPGA prototype, and ATE vector bring-up in a senior hardware-aware software verification context.

Location: San Jose, Irvine

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Architect block- and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed-signal interfaces.
•Develop test plans and coverage metrics from specifications and write block- and chip-level tests using mixed-signal simulations (AMS, Spice).
•Debug RTL and Gate simulations and collaborate with design engineers to verify fixes.
•Write diagnostics for validation of FPGA prototypes (pre-tapeout) and ASIC, and replicate silicon bugs in simulations with fixes or SW workarounds.
•Convert verification tests to test patterns and assist Test Engineers on ATE vector bring-up.

Pay and Benefits

Salary: USD 141,300 - 226,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceVision401kEquityEspp

Key Requirements

•Bachelor in Engineering with 12+ years of related experience; or Masters in Engineering with 10+ years; or PhD in Engineering with 7+ years of related experience
•MS or PhD is preferred
•Experience architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces
•Thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests
•Ability to take customer requirements to verify full chip design and architecture

Experience:12+ yearsSemiconductorsHardware verification

Education:Bachelor's

Skills:Problem-solvingCommunication

Tech Stack:HVLUVMAMSSpiceUPFFPGAATERTLGate simulationsLow power verification

Company Brief

Broadcom

Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Irvine, United States

Founded: 1991

Website LinkedIn

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Broadcom

3 months ago

Senior ASIC DV Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 3 hours agoStatus: Live

Job Summary

Location: San Jose, Irvine

Workplace: Onsite

Employment Type: Full time

Job Function: Hardware, Embedded & Systems Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Architect block- and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed-signal interfaces.
•Develop test plans and coverage metrics from specifications and write block- and chip-level tests using mixed-signal simulations (AMS, Spice).
•Debug RTL and Gate simulations and collaborate with design engineers to verify fixes.
•Write diagnostics for validation of FPGA prototypes (pre-tapeout) and ASIC, and replicate silicon bugs in simulations with fixes or SW workarounds.
•Convert verification tests to test patterns and assist Test Engineers on ATE vector bring-up.

Pay and Benefits

Salary: USD 141,300 - 226,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceVision401kEquityEspp

Key Requirements

•Bachelor in Engineering with 12+ years of related experience; or Masters in Engineering with 10+ years; or PhD in Engineering with 7+ years of related experience
•MS or PhD is preferred
•Experience architecting block and full-chip verification environments using HVLs (UVM) and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces
•Thorough knowledge of mixed-signal simulations (AMS, Spice, etc), developing test plans and coverage metrics from specifications and writing block and chip-level tests
•Ability to take customer requirements to verify full chip design and architecture

Experience:12+ yearsSemiconductorsHardware verification

Education:Bachelor's

Skills:Problem-solvingCommunication

Tech Stack:HVLUVMAMSSpiceUPFFPGAATERTLGate simulationsLow power verification

Company Brief

Broadcom

Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Irvine, United States

Founded: 1991

Website LinkedIn