Lead DFT Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: QA, Test & Release EngineeringEducation: bachelorsSkills: ["Detail-oriented","Accurate","Communication","Problem-solving"]

Work on AMD’s DFT team to achieve first-pass silicon success by partnering with DFT architecture, IP and physical design, and product engineers. Own scan architecture understanding, scan insertion, and ATPG pattern generation (stuck-at, transition ATPG, IDDQ). Run GLS and timing/power-aware simulations, analyze test coverage and cost, perform yield root-cause debug and recovery, and support post-silicon bring-up through phasing closure across multiple SOC tape-outs.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
1 month ago

Lead DFT Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Work on AMD’s DFT team to achieve first-pass silicon success by partnering with DFT architecture, IP and physical design, and product engineers. Own scan architecture understanding, scan insertion, and ATPG pattern generation (stuck-at, transition ATPG, IDDQ). Run GLS and timing/power-aware simulations, analyze test coverage and cost, perform yield root-cause debug and recovery, and support post-silicon bring-up through phasing closure across multiple SOC tape-outs.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering

Key Responsibilities

  • •Collaborate with the DFT architecture, IP design, physical design, and product engineering teams to deliver first-pass silicon success.
  • •Apply scan insertion methods and generate ATPG patterns for stuck-at, transition ATPG, and IDDQ.
  • •Perform GLS plus timing and power-aware simulations to support design validation.
  • •Drive test coverage and test cost reduction analysis, and conduct yield analysis with root-cause debug and recovery.
  • •Lead post-silicon bring-up planning, coordination, and execution, including phasing closure and production enablement across multiple SOC tape-outs.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •Strong understanding of scan architecture and scan features.
  • •Experience with scan insertion and ATPG pattern generation for stuck-at, transition ATPG, and IDDQ pattern generation.
  • •Hands-on capability with GLS and timing and power-aware simulations.
  • •Ability to analyze test coverage and reduce test cost, plus perform yield analysis and debug for root-cause recovery.
  • •Bachelor’s or master’s degree in Electronics/VLSI/Electrical Engineering.
Education:Bachelor's in Electronics/VLSI/Electrical Engineering
Skills:Detail-orientedAccurateCommunicationProblem-solving
Languages:En-us
Tech Stack:Scan architectureScan featuresScan insertionATPG pattern generationStuck-atTransition ATPGIDDQ pattern generationGLSTiming-aware simulationsPower-aware simulationsTest coverageTest cost reduction analysisYield analysisSilicon debugMentor testkompressSynopsys TetramaxDFTMAXVCSPerl/Shell scriptingVerilog RTL design

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn