DFT- ATPG Engineer

Work on AMD’s DFT team to achieve first-pass silicon success by partnering with DFT architecture, IP and physical design, and product engineers. Own scan architecture understanding, scan insertion, and ATPG pattern generation (stuck-at, transition ATPG, IDDQ). Run GLS and timing/power-aware simulations, analyze test coverage and cost, perform yield root-cause debug and recovery, and support post-silicon bring-up through phasing closure across multiple SOC tape-outs.