Memory Layout Manager

Intel
Bengaluru
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 15+ yearsEducation: bachelorsSkills: ["Emotional intelligence","Interpersonal communication","Leadership","Collaboration","Technical excellence"]

Lead and mentor a team of layout engineers delivering SRAM/RF/ROM/CAM memory compiler designs for Intel’s FinFETs and GAA technologies. Own compiler-friendly floorplanning, placement/routing templates, and physical sign-off covering DRC, LVS, yield, DFM, density, parasitic extraction, and noise/reliability (EM/IR). Collaborate across circuit design, tilers, and foundry teams, modernize layout methodology with AI/ML and automation flows using SKILL, Python, and Tcl, and drive tape-out quality and performance targets.

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Intel
Intel
2 days ago

Memory Layout Manager

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Last checked: 19 hours agoStatus: Live

Job Summary

Lead and mentor a team of layout engineers delivering SRAM/RF/ROM/CAM memory compiler designs for Intel’s FinFETs and GAA technologies. Own compiler-friendly floorplanning, placement/routing templates, and physical sign-off covering DRC, LVS, yield, DFM, density, parasitic extraction, and noise/reliability (EM/IR). Collaborate across circuit design, tilers, and foundry teams, modernize layout methodology with AI/ML and automation flows using SKILL, Python, and Tcl, and drive tape-out quality and performance targets.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Manager level

Key Responsibilities

  • •Lead and mentor layout design engineers to deliver world-class memory compiler designs on FinFET/GAA technologies, aligned with goals and timelines.
  • •Oversee design, development, modification, analysis, and verification of memory compiler layout designs.
  • •Provide technical guidance across analog, digital, memory, and standard cell layout methodologies, compilers, tools, and flows.
  • •Set objectives and drive execution by leveraging AI-driven EDA tools and generative machine learning to automate repetitive layout tasks and improve placement/routing.
  • •Manage resources and performance to meet project execution and performance targets, while fostering a supportive, collaborative environment.

Key Requirements

  • •Bachelor’s or Master’s degree in Electronics, Electrical, or VLSI Engineering, with 15+ years of deep technical experience in memory compiler layout design and management.
  • •Successful tape-outs on cutting-edge foundry geometries (e.g., 3nm, 2nm, or below) using Cadence Virtuoso, Siemens Calibre, and Synopsys IC Validator.
  • •Expert proficiency in driving layout methodologies and flows for analog, digital, memory, and standard cell designs.
  • •Proven ability to lead teams and manage complex projects effectively.
  • •Strong emotional intelligence and exceptional interpersonal communication to scale and lead high-performing engineering teams in a fast-paced environment.
Experience:15+ yearsSemiconductorsEDAFoundryVLSIMemory compilers
Education:Bachelor's in Electronics, Electrical, or VLSI Engineering
Skills:Emotional intelligenceInterpersonal communicationLeadershipCollaborationTechnical excellence
Tech Stack:FinFETGAASRAMRFROMCAMEDASKILLPythonTclCadence VirtuosoSiemens CalibreSynopsys IC ValidatorDRCLVSDFMParasitic extractionNoise reliabilityEMIR

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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