Physical Design Lead

AMD
Bengaluru
Workplace: OnsiteFull timeINR 4,860,800 - 6,944,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: mastersSkills: ["Communication","Detail-oriented","Team collaboration","Presentation","Inter-communication"]

Lead the physical design implementation team within AMD’s CT India organization to drive first-pass silicon success. Own backend convergence from RTL through PnR, timing, verification, and signoff, including IP integration and full-chip/GDS delivery. Collaborate with architects, IP teams, CAD/EDA vendors, and PD/STA engineers to improve PPA and execution quality while providing technical direction and support to silicon design engineers.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
1 month ago

Physical Design Lead

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Lead the physical design implementation team within AMD’s CT India organization to drive first-pass silicon success. Own backend convergence from RTL through PnR, timing, verification, and signoff, including IP integration and full-chip/GDS delivery. Collaborate with architects, IP teams, CAD/EDA vendors, and PD/STA engineers to improve PPA and execution quality while providing technical direction and support to silicon design engineers.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead the physical design implementation team for highly complex tile implementation and convergence.
  • •Drive GDS delivery from RTL, including signoff and physical verification.
  • •Collaborate cross-functionally to improve PPA through continuous implementation and convergence improvements.
  • •Manage understanding and execution of horizontal sign-off flows (e.g., VCLP, formal equivalence, low power checks) and timing convergence for tiles and full chip.
  • •Provide technical direction, guidance, and support to the engineering team; collaborate with CAD/EDA vendors to strengthen PD closure methodology.

Pay and Benefits

Salary: INR 4,860,800 - 6,944,000 annually

Key Requirements

  • •B.Tech/M.Tech/MS/Ph.D. in Computer, Electronics, or Electrical Engineering.
  • •15+ years of physical design experience from RTL to GDS, including STA, physical verification, timing signoff, and tapeout.
  • •Ability to drive/manage projects from RTL to GDS and manage more than 4 tape-outs.
  • •Block-level place-and-route expertise, including floorplanning, timing closure, and physical verification.
  • •Proficiency with industry-standard physical design EDA tools and low-power/verification signoff techniques.
Experience:15+ yearsPhysical designRTL to GDSSTAPhysical verificationTiming signoffTapeoutIP integrationChipletsSoC
Education:Master's in Computer/Electronics/Electrical Engineering
Skills:CommunicationDetail-orientedTeam collaborationPresentationInter-communication
Languages:En-us
Tech Stack:Fusion compilerICC2PrimetimeRedhawkPTPXVCLPFormal EquivalenceLow Power ChecksPerlTCLShellPythonVerilogVHDLIR&EMVSILECLEC/Formal Equivalence Check

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn