Design Verification Engineer

Broadcom
United States, San Diego, Colorado
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["Problem-solving","Debugging","Communication","Planning","Adaptability"]

Own verification planning and environment architecture for complex digital and mixed-signal ASIC IP blocks. Build reusable testbenches and functional models using SystemVerilog, UVM, UVM agents, checkers, and SystemVerilog Assertions, then drive coverage analysis, closure, and debug at RTL and gate level. Collaborate with design teams, EDA vendors, and potentially emulation/FPGA platforms to evaluate advanced verification methodologies and improve verification flows.

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FursaFursa
Broadcom
Broadcom
1 month ago

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 31 days agoStatus: Live

Job Summary

Own verification planning and environment architecture for complex digital and mixed-signal ASIC IP blocks. Build reusable testbenches and functional models using SystemVerilog, UVM, UVM agents, checkers, and SystemVerilog Assertions, then drive coverage analysis, closure, and debug at RTL and gate level. Collaborate with design teams, EDA vendors, and potentially emulation/FPGA platforms to evaluate advanced verification methodologies and improve verification flows.
Location: United States, San Diego, Colorado
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Define verification plans and verification environment architecture for complex digital and mixed-signal IP blocks.
  • •Develop test cases and testbench components, including reusable functional models for block, system, and ASIC level verification.
  • •Drive coverage analysis and closure, and analyze and debug simulation failures at RTL and gate level.
  • •Evaluate and lead adoption of advanced verification methodologies/flows, potentially involving emulation and FPGA prototyping platforms.
  • •Work closely with design teams and EDA vendors to complete modeling and verification tasks.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEquityPaid Leave

Key Requirements

  • •12+ years of experience in verification concepts and architectures for complex digital and mixed-signal circuits
  • •Experience verifying designs at the block and system levels
  • •Experience with complex digital and mixed-signal circuits (PLL, DLL, ADC, DAC)
  • •Strong debugging skills for RTL and gate-level netlists, including RTL/gate-level analysis and schematic understanding for analog/MXS circuits
  • •Proficiency with SystemVerilog, UVM, and advanced verification methodologies, including UVM agents, checkers, and SystemVerilog Assertions
Experience:12+ yearsASICMixed-signalEmbedded IP
Education:Bachelor's in Electrical Engineering / Computer Engineering
Skills:Problem-solvingDebuggingCommunicationPlanningAdaptability
Tech Stack:SystemVerilogUVMSVASynopsysCadenceMentorPerlPythonTclDesignSyncGitSystemVerilog AssertionsUVM agentsUVM checkersBehavioral modelsRandom testingDirected testingCoverage analysisRTLGate-level netlists

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn