Lead SOC RTL Design Engineer

Lead the SoC RTL design efforts at SSIR, overseeing 9-12 years of experience in IP design and SOC subsystems. Architect SOC blocks and sub-systems, define interconnects (AXI/AHB/APB), and drive front-end design planning, timing closure, and verification. Manage a 4-5 engineer team, mentor on high/low-speed protocols (SPI/I2C/I3C/UART/PWM), and coordinate IPs such as UCIe, Ethernet and UFS.