FPGA/ASIC Design Engineer (Silicon Engineering)

SpaceX
Redmond, Irvine
Workplace: OnsiteFull timeUSD 125,000 - 175,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 1+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","VHDL","Python","C","C++","Bash","AXI","AHB","APB","Verilog/SystemVerilog","Xilinx Vivado","Altera Quartus II","VCS","Questa","IES","Spyglass"]

Design and optimize ASICs and FPGAs for SpaceX’s Starlink projects, contributing to the full design lifecycle from architecture through validation. Collaborate with cross-functional teams and software engineers, and develop production software tooling to support on-orbit and lab verification of high-performance silicon.

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FursaFursa
SpaceX
SpaceX
3 months ago

FPGA/ASIC Design Engineer (Silicon Engineering)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Design and optimize ASICs and FPGAs for SpaceX’s Starlink projects, contributing to the full design lifecycle from architecture through validation. Collaborate with cross-functional teams and software engineers, and develop production software tooling to support on-orbit and lab verification of high-performance silicon.
Location: Redmond, Irvine
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/SystemVerilog
  • •Optimize designs for power, performance and area
  • •Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams
  • •Contribute to continual improvements to our designs by building physical and digital tools to analyze data collected on orbit and in the lab
  • •Engage in high-level architectural design for test systems to support FPGA/ASIC validation, generational interoperability, and integration with DSP/communications subsystems for comprehensive lab and on-orbit verification.

Pay and Benefits

Salary: USD 125,000 - 175,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceVisionDental401kEquityPaid LeavePaid Holidays

Key Requirements

  • •Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
  • •1+ years of RTL design experience using SystemVerilog, Verilog or VHDL
  • •Strong fundamentals in electrical engineering and debugging PCBs with test equipment
Experience:1+ yearsSpaceAerospaceTelecommunications
Education:Bachelor's
Skills:VerilogSystemVerilogVHDLPythonCC++BashAXIAHBAPBVerilog/SystemVerilogXilinx VivadoAltera Quartus IIVCSQuestaIESSpyglass
Languages:English
Tech Stack:VerilogSystemVerilogVHDLPythonCC++BashXilinx VivadoAltera Quartus IIVCSQuestaIESSpyglass

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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Glassdoor: 4.2
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