AE Group Director

Cadence Design Systems
Anywhere
Workplace: OnsiteFull timeFunction: SalesExperience: 20+ yearsSkills: ["Program management","Engagement management","Teamwork","English communication"]

Lead digital IC implementation activities, bringing 20+ years of experience across floorplan, power-plan, placement, CTS, routing, and SI/STA signoff. Drive hierarchical, timing-driven, SI prevention, and low-power place-and-route initiatives, ensuring successful execution of advanced flows. Work with SOC-E and STA (ETS or PrimeTime-SI), including RC extraction and LEF generation via Abstract generator. Bring strong Linux and Tcl knowledge and solid program/engagement management skills.

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Cadence Design Systems
Cadence Design Systems
2 months ago

AE Group Director

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Lead digital IC implementation activities, bringing 20+ years of experience across floorplan, power-plan, placement, CTS, routing, and SI/STA signoff. Drive hierarchical, timing-driven, SI prevention, and low-power place-and-route initiatives, ensuring successful execution of advanced flows. Work with SOC-E and STA (ETS or PrimeTime-SI), including RC extraction and LEF generation via Abstract generator. Bring strong Linux and Tcl knowledge and solid program/engagement management skills.
Location: Anywhere
Workplace: Onsite
Employment Type: Full time
Job Function: Sales
Seniority: Sr. Director level

Key Responsibilities

  • •Run advanced hierarchical, timing-driven SI prevention and low-power place-and-route processes.
  • •Oversee digital IC implementation activities including floorplan, power-plan, placement, CTS, routing, and SI/STA signoff.
  • •Apply expertise with SOC-E and STA (ETS or PrimeTime-SI) throughout signoff workflows.
  • •Support RC extraction and LEF generation using Abstract generator.
  • •Manage program execution and engagement effectively while partnering as an effective team player.

Key Requirements

  • •20+ years of experience in digital IC implementation, including floorplan, power-plan, placement, CTS, routing, and SI & STA signoff.
  • •Hands-on experience running advanced hierarchical, timing-driven SI prevention and low-power place-and-route projects.
  • •Familiarity with SOC-E, STA (ETS or PrimeTime-SI), RC extraction, and LEF generation with Abstract generator.
  • •Knowledge of Linux and Tcl.
  • •Good program/engagement management skills and good command of English (written or oral).
Experience:20+ yearsDigital IC implementationPlace-and-routeStatic timing analysisSI prevention
Skills:Program managementEngagement managementTeamworkEnglish communication
Languages:English
Tech Stack:LinuxTclSOC-ESTAETSPrimeTime-SIRC extractionLEF generationAbstract generatorFloorplanPower-planPlacementCTSRoutingSI signoff

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
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