ASIC Architect R&D (F/H) (Échirolles, FR)
Grenoble, Sophia Antipolis
Workplace: OnsiteFull timeFunction: Architecture & Urban PlanningExperience: 5+ yearsEducation: mastersSkills: ["Communication","Teamwork","Autonomy"]Senior hardware architect in an HPC/R&D context, shaping next-generation ASIC features for AI and HPC workloads. Collaborates with RTL, verification, and software teams to define high-performance interconnect and accelerator architectures, proposes RDMA-based innovations for Ethernet/HPC, produces architecture specifications and cost/performance projections, and supports ASIC design flow across multiple European research centers and partner sites.
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