Senior Design Verification Engineer
Belgrade
Workplace: HybridFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsSkills: ["SystemVerilog","UVM","Emulation","Scripting","AMBA","PCIe","SPI","I2C","JTAG","CPU"]Senior Design Verification Engineer responsible for developing and maintaining DV infrastructure for ASIC verification of Cisco Silicon One chips, using SystemVerilog/UVM. Collaborates with architects, designers, and global teams across emulation and simulation stages, ensuring complete verification coverage and supporting post-silicon validation efforts in a hybrid Belgrade, Serbia team.
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