ASIC DFT Technical Leader

Cisco
San Jose, Austin
Workplace: HybridFull timeUSD 186,900 - 267,700 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 10+ yearsEducation: mastersSkills: ["Debugging","Problem-solving"]

Lead ASIC DFT efforts within the Silicon One development organization, partnering with front-end RTL and backend physical design teams to establish DFT requirements early. Drive the DFT and quality process through implementation, post-silicon validation, and signoff-related activities while contributing to next-generation networking chip development.

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FursaFursa
Cisco
Cisco
1 month ago

ASIC DFT Technical Leader

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Last checked: 2 hours agoStatus: Live

Job Summary

Lead ASIC DFT efforts within the Silicon One development organization, partnering with front-end RTL and backend physical design teams to establish DFT requirements early. Drive the DFT and quality process through implementation, post-silicon validation, and signoff-related activities while contributing to next-generation networking chip development.
Location: San Jose, Austin
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Sr. Manager level

Key Responsibilities

  • •Work in the Silicon One development organization as an ASIC Technical Leader for DFT, driving DFT requirements early in the design cycle.
  • •Partner with front-end RTL teams and backend physical design teams to understand chip architecture and align DFT needs.
  • •Lead the DFT and quality process across the entire implementation flow and post-silicon validation phases.
  • •Gain exposure to physical design signoff activities while supporting next-generation networking chip development.
  • •Contribute to post-silicon validation and debug activities using DFT patterns and related tooling.

Pay and Benefits

Salary: USD 186,900 - 267,700 annually
Perks:Health InsuranceDentalVision401kPaid ParentalPaid Holidays

Key Requirements

  • •Bachelor's or Master's degree in Electrical or Computer Engineering with at least 10 years of experience.
  • •Experience in DFT, test, and silicon engineering, including JTAG protocols, scan, and BIST architectures (including memory BIST and boundary scan).
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, Tessent, and PrimeTime.
  • •Experience with gate-level simulation and debugging with VCS and other simulators.
  • •Post-silicon validation/debug experience, including the ability to work with ATE patterns and P1687.
Experience:10+ yearsASICDFTSilicon engineering
Education:Master's in Electrical or Computer Engineering
Skills:DebuggingProblem-solving
Tech Stack:RTLDFTJTAGScanBISTMemory BISTBoundary scanATPGTestMaxTetramaxTessentPrimeTimeGate-level simulationVCSVerilogSystemVerilogATE patternsP1687EDA

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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