6 months ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 55 minutes agoStatus: Live

Job Summary

Seeking a Performance Modeling Engineer to develop cycle-level performance models for next-generation DDR memory controller architectures, perform architectural tradeoff analysis, and enable data-driven design decisions. Work with hardware modeling (C++/SystemC/TLM) and Python to support RTL configurations, characterize throughput/latency, and create synthetic memory traffic traces for real-world workloads.

Location: Pune

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Develop cycle-level performance models in SystemC or C++
•Correlate performance models to match RTL configurations and traffic conditions
•Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
•Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
•Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Key Requirements

•BE/B.Tech/ME/M.Tech in ECE, E&T C, CS or similar
•8+ years of experience in hardware modeling, functional or performance
•Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
•Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
•Additional: Understand RTL-Verilog, SV, UVM and memory protocols and timing (DDR4, DDR5, LP4, LP5)

Experience:8+ yearsMemory systemsHardware modelingDDR memory controllerSoC

Education:Bachelor's in ECE

Skills:Problem-solvingTeamwork

Tech Stack:C++SystemCTLMPythonVerilogDDR4DDR5

Company Brief

Cadence Design Systems

Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor

Loading job details...

Preparing the role view and application actions.

Cadence Design Systems

6 months ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 55 minutes agoStatus: Live

Job Summary

Location: Pune

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Develop cycle-level performance models in SystemC or C++
•Correlate performance models to match RTL configurations and traffic conditions
•Work with Memory Architects to understand feature requirements, architectural specifications and implement in the model
•Analyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices
•Develop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks

Key Requirements

•BE/B.Tech/ME/M.Tech in ECE, E&T C, CS or similar
•8+ years of experience in hardware modeling, functional or performance
•Strong coding skills in C++, SystemC and Transaction Level Modeling (TLM)
•Basic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs
•Additional: Understand RTL-Verilog, SV, UVM and memory protocols and timing (DDR4, DDR5, LP4, LP5)

Experience:8+ yearsMemory systemsHardware modelingDDR memory controllerSoC

Education:Bachelor's in ECE

Skills:Problem-solvingTeamwork

Tech Stack:C++SystemCTLMPythonVerilogDDR4DDR5

Company Brief

Cadence Design Systems

Industry: Developer Tools

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: San Jose, United States

Founded: 1988

Glassdoor: 3.9

Website LinkedIn Glassdoor