Static Timing Analysis / Full Chip Timing Engineer

AMD
Markham
Workplace: OnsiteFull timeCAD 135,800 - 232,800 annuallyFunction: Hardware, Embedded & Systems EngineeringSkills: ["Communication","Root-cause analysis","Documentation","Technical analysis"]

Own full-chip static timing analysis (STA) and timing closure for complex SoC designs, driving convergence from early netlist through final signoff. Partner with PnR, synthesis/DFT, and CAD teams to resolve timing violations, execute multi-corner/multi-mode convergence, and manage SI/crosstalk and OCV/POCV impacts. Lead clock architecture strategy, define STA methodology and signoff criteria, and build automation to streamline signoff checks and QoR tracking.

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FursaFursa
AMD
AMD
1 day ago

Static Timing Analysis / Full Chip Timing Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 43 minutes agoStatus: Live

Job Summary

Own full-chip static timing analysis (STA) and timing closure for complex SoC designs, driving convergence from early netlist through final signoff. Partner with PnR, synthesis/DFT, and CAD teams to resolve timing violations, execute multi-corner/multi-mode convergence, and manage SI/crosstalk and OCV/POCV impacts. Lead clock architecture strategy, define STA methodology and signoff criteria, and build automation to streamline signoff checks and QoR tracking.
Location: Markham
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering

Key Responsibilities

  • •Own full-chip static timing analysis and timing closure from early design netlist through final signoff.
  • •Drive multi-corner/multi-mode timing convergence across PVT corners and modes.
  • •Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related impacts; lead root-cause analysis and ECO-driven fixes.
  • •Guide clock architecture strategy, including clock tree methodology and skew/latency target definition.
  • •Define common STA methodology and signoff criteria; build automation to streamline signoff checks, QoR tracking, and dashboards.

Pay and Benefits

Salary: CAD 135,800 - 232,800 annually

Key Requirements

  • •BS/MS/PhD in Electrical Engineering, Computer Engineering, or a related field.
  • •Full-chip timing experience (preferred).
  • •Own full-chip timing closure across setup, hold, and DRV signoff activities.
  • •Analyze and resolve SI/crosstalk, OCV/POCV, and clock-related impacts; perform root-cause analysis of timing violations.
  • •Generate, validate, and hand off ECOs to PnR PD teams; verify legalization and post-ECO QoR.
Experience:SoCTiming analysis
Education:
Skills:CommunicationRoot-cause analysisDocumentationTechnical analysis
Tech Stack:Static timing analysisSTATiming closureTiming convergenceSetupHoldDRVMulti-corner multi-modeMMMCPVTSI/crosstalkOCV/POCVClock skewClock jitterUncertaintyECOPnRSynthesisDFTCAD

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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