SoC Physical Design Senior Manager, HBM

Micron Technology
United States
Workplace: OnsiteFull timeUSD 177,000 - 309,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: bachelorsSkills: ["Mentorship","Leadership","Communication","Debugging","Collaboration"]

Lead a hands-on physical design team in the Heterogeneous Integration Group to implement advanced HBM SoC designs from netlist to GDSII. Drive PPA-focused floorplanning, placement, CTS, routing, and timing closure across multi-mode/multi-corner scenarios, partnering with RTL, DFT, IP, packaging, and manufacturing. Own physical signoff (DRC/LVS, IR drop/EM, timing) and tapeout execution, while improving flow productivity with scripting/automation and AI/LLM-driven workflows.

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Micron Technology
Micron Technology
1 week ago

SoC Physical Design Senior Manager, HBM

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Job Summary

Lead a hands-on physical design team in the Heterogeneous Integration Group to implement advanced HBM SoC designs from netlist to GDSII. Drive PPA-focused floorplanning, placement, CTS, routing, and timing closure across multi-mode/multi-corner scenarios, partnering with RTL, DFT, IP, packaging, and manufacturing. Own physical signoff (DRC/LVS, IR drop/EM, timing) and tapeout execution, while improving flow productivity with scripting/automation and AI/LLM-driven workflows.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Recruit, develop, and mentor a team of physical design and physical verification engineers delivering HBM base die products.
  • •Plan project resourcing and timelines, prioritizing across assignments to meet aggressive delivery schedules.
  • •Drive physical implementation (floorplanning, placement, CTS, routing, physical optimization) and timing closure across multi-mode/multi-corner scenarios.
  • •Collaborate on clocking/reset strategy, power architecture, and SoC integration requirements; integrate complex IP with timing/power integrity focus.
  • •Coordinate physical signoff (DRC/LVS/IR drop/EM/timing), support tapeout execution (checklists, ECO flows, signoff reviews), and improve productivity via scripting/automation and AI/LLM-driven workflows.

Pay and Benefits

Salary: USD 177,000 - 309,000 annually
Equity and Bonus:Equity
Perks:Health InsurancePaid LeaveLearning BudgetWellness StipendEquity

Key Requirements

  • •Strong SoC physical design experience from netlist to GDSII on advanced nodes for complex designs.
  • •Proficiency with industry EDA tools such as Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, and Siemens Calibre (or equivalent).
  • •Solid STA fundamentals, clocking, constraints (SDC), and common closure techniques (e.g., buffering, path shaping, useful skew).
  • •Experience with power intent/delivery concepts (e.g., UPF/CPF), including power grid and power gating implications.
  • •Familiarity with physical verification and signoff concepts including DRC/LVS/ERC and parasitic extraction awareness.
Experience:15+ yearsSemiconductorSoCHBMDRAMEDAFoundry
Education:Bachelor's in Electrical Engineering, Computer Engineering, or a related field
Skills:MentorshipLeadershipCommunicationDebuggingCollaboration
Tech Stack:HBMGDSIICadence InnovusCadence TempusSynopsys ICC2PrimeTimeSiemens CalibreSTASDCUPFCPFDFTDRCLVSERCParasitic extractionMMMCCTSTiming closureIR drop

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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Glassdoor: 3.7
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