3 days ago

Power Integrity Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Own power integrity methodology for high-power PCB and system designs, guiding robust power delivery to high-performance ASICs across operating conditions. Lead pre- and post-layout PDN analysis, DC IR-drop/current density and AC impedance modeling from VRM to package/die, and develop VRM models to validate transient behavior and multiphase performance. Collaborate across power, PCB layout, ASIC/package, and mechanical teams, support bring-up debugging, and improve modeling via simulation-to-hardware correlation.

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Energy & Utilities Operations

Seniority: Mid level

Key Responsibilities

•Perform pre- and post-layout PDN analysis for high-current ASIC power rails, including target impedance profiling and plane resonance analysis.
•Run DC IR-drop and current density simulations and define copper weight, plane shapes, via stitching, and layer allocation requirements.
•Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the decoupling network.
•Develop and validate VRM models, analyzing load transient response, AVP/load-line behavior, and multiphase converter performance.
•Drive PI design rule checks for compliance, collaborate with layout teams and partner groups, and support bring-up debug with corrective actions.

Pay and Benefits

Perks:Health InsuranceDentalVisionHousing SubsidyRelocation SupportWellness Stipend

Key Requirements

•B.S. or M.S. in Electrical Engineering (or closely related).
•5+ years of hands-on PI experience on high-current, high-performance designs for ASIC/CPU/GPU power delivery.
•Proficiency with PI EDA tools such as Ansys SIwave and Cadence Sigrity PowerDC/PowerSI/OptimizePI.
•Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.
•Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.

Experience:Data centerAI/ML acceleratorNetworkingHigh-performance computing (HPC)ASIC/CPU/GPU power delivery

Education:Bachelor's in Electrical Engineering

Skills:CollaborationDocumentationRoot-cause analysisProblem-solving

Tech Stack:Ansys SIwaveCadence AllegroCadence Sigrity PowerDCCadence Sigrity PowerSICadence Sigrity OptimizePIPowerDC/PowerSIPowerSIwavePythonMATLAB

Company Brief

Etched

Designs transformer‑specialized AI inference ASICs (product: Sohu) to accelerate large‑language‑model workloads, working with TSMC for fabrication and targeting energy‑efficient inference performance.

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor

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Etched

3 days ago

Power Integrity Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 21 hours agoStatus: Live

Job Summary

Location: San Jose

Workplace: Onsite

Employment Type: Full time

Job Function: Energy & Utilities Operations

Seniority: Mid level

Key Responsibilities

•Perform pre- and post-layout PDN analysis for high-current ASIC power rails, including target impedance profiling and plane resonance analysis.
•Run DC IR-drop and current density simulations and define copper weight, plane shapes, via stitching, and layer allocation requirements.
•Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the decoupling network.
•Develop and validate VRM models, analyzing load transient response, AVP/load-line behavior, and multiphase converter performance.
•Drive PI design rule checks for compliance, collaborate with layout teams and partner groups, and support bring-up debug with corrective actions.

Pay and Benefits

Perks:Health InsuranceDentalVisionHousing SubsidyRelocation SupportWellness Stipend

Key Requirements

•B.S. or M.S. in Electrical Engineering (or closely related).
•5+ years of hands-on PI experience on high-current, high-performance designs for ASIC/CPU/GPU power delivery.
•Proficiency with PI EDA tools such as Ansys SIwave and Cadence Sigrity PowerDC/PowerSI/OptimizePI.
•Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.
•Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.

Experience:Data centerAI/ML acceleratorNetworkingHigh-performance computing (HPC)ASIC/CPU/GPU power delivery

Education:Bachelor's in Electrical Engineering

Skills:CollaborationDocumentationRoot-cause analysisProblem-solving

Tech Stack:Ansys SIwaveCadence AllegroCadence Sigrity PowerDCCadence Sigrity PowerSICadence Sigrity OptimizePIPowerDC/PowerSIPowerSIwavePythonMATLAB

Company Brief

Etched

Industry: Hardware Devices

Company Size: Medium (51 to 250 employees)

Growth: Early Stage Startup

Valuation: Unicorn (USD 1B+)

Funding: Series A

Headquarters: San Jose, United States

Founded: 2022

Website LinkedIn Glassdoor