Staff Silicon Design Engineer

AMD
Serbia
Workplace: HybridFull timeRSD 5,002,550 - 7,146,500 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Self-driven","Detail-oriented","Ownership","Communication","Cross-functional collaboration"]

Lead and execute verification of complex SoC subsystems, owning verification strategy, test planning, execution, and sign-off metrics across one or more subsystem test suites. Build and extend UVM/SystemVerilog testbenches with coverage-driven verification, integrate multiple IPs, and analyze coverage gaps. Debug RTL and system-level issues using waveforms, logs, and assertions while collaborating with cross-functional RTL, architecture, firmware, emulation, and performance teams.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
1 day ago

Staff Silicon Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Lead and execute verification of complex SoC subsystems, owning verification strategy, test planning, execution, and sign-off metrics across one or more subsystem test suites. Build and extend UVM/SystemVerilog testbenches with coverage-driven verification, integrate multiple IPs, and analyze coverage gaps. Debug RTL and system-level issues using waveforms, logs, and assertions while collaborating with cross-functional RTL, architecture, firmware, emulation, and performance teams.
Location: Serbia
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Define verification strategy and test plans for assigned subsystem(s), including coverage goals, corner cases, and sign-off criteria.
  • •Develop UVM/SystemVerilog testbenches, sequences, scoreboards, coverage models, checkers, and assertions (SVA).
  • •Drive constrained-random and directed testing, analyze coverage gaps, and create tests to close functional, code, and assertion coverage metrics.
  • •Integrate multiple IPs and verify interactions at the subsystem level (e.g., coherency, ordering, QoS, virtual channels, power/clock/reset behavior, security/isolation).
  • •Debug complex issues across RTL, testbench, and interfaces; root-cause failures using waveforms, logs, and assertions.

Pay and Benefits

Salary: RSD 5,002,550 - 7,146,500 annually

Key Requirements

  • •Strong background in SoC or subsystem verification with hands-on experience in UVM/SystemVerilog-based environments.
  • •Solid understanding of complex SoC architectures, including memory/cache hierarchies, coherency protocols, interconnects, and high-speed interfaces such as PCIe and DDR.
  • •Proven ability to define verification strategies, develop reusable testbenches, and drive coverage-driven verification to sign-off.
  • •Experienced in debugging complex RTL and system-level issues using waveforms, logs, and assertions.
  • •Comfortable collaborating cross-functionally with RTL design, architecture, firmware, emulation, and performance teams.
Skills:Self-drivenDetail-orientedOwnershipCommunicationCross-functional collaboration
Tech Stack:SoCSubsystem verificationUVMSystemVerilogRTLCoverage-driven verificationReusable testbenchesConstrained-randomDirected testingScoreboardsCoverage modelsCheckersAssertionsSVACI/regressionWaveformsLogsPCIeDDRMemory/cache

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn