Senior SoC Design Engineer

FuriosaAI
Seoul
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Collaboration","Communication","Cross-team coordination"]

Design and evaluate SoC architecture based on requirements, target performance, and system specifications. Define micro-architecture in documentation, implement RTL, and support top-level integration with timing closure, lint checks, and synthesis. Collaborate with verification, physical implementation, and silicon bring-up teams, delivering verification plans and incorporating physical/PnR considerations into RTL. Participate in system-level verification during bring-up.

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FursaFursa
FuriosaAI
FuriosaAI
1 day ago

Senior SoC Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Design and evaluate SoC architecture based on requirements, target performance, and system specifications. Define micro-architecture in documentation, implement RTL, and support top-level integration with timing closure, lint checks, and synthesis. Collaborate with verification, physical implementation, and silicon bring-up teams, delivering verification plans and incorporating physical/PnR considerations into RTL. Participate in system-level verification during bring-up.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Decide SoC architecture by understanding requirements, target performance, and system specifications.
  • •Define micro-architecture in document form and design RTL based on it.
  • •Perform top-level integration and execute timing closure, lint checks, and synthesis; collaborate with other teams.
  • •Collaborate with the Design Verification team to write verification plans and achieve coverage goals.
  • •Collaborate with Physical Implementation and Silicon bring-up teams, incorporating PnR physical issues into RTL and participating in bring-up/system-level verification.

Key Requirements

  • •Bachelor’s in Electrical Engineering or Computer Engineering (or a Master’s with 5+ years RTL design).
  • •7+ years RTL design experience (or 5+ years with a Master’s).
  • •Experience designing SoC system IP and integrating multiple IPs at System/Chiptop level.
  • •Subsystem or top-level design experience, including data center or large-scale SoC design experience.
  • •Strong understanding of AMBA bus protocol and bus interfaces, including clock domain crossing (CDC).
Experience:5+ years
Education:Bachelor's in Electrical Engineering or Computer Engineering
Skills:CollaborationCommunicationCross-team coordination
Tech Stack:SoC architectureMicro-architectureRTL designTiming closureLint checkSynthesisRTLSubsystem integrationTop-level integrationVerification planCoverage goalPnRPhysical implementationSilicon bring-upSystem/Chiptop integrationAMBA bus protocolBus interfaceClock Domain Crossing (CDC)EDA toolsPower estimation

Company Brief

FuriosaAI
Designs and develops data‑center AI inference accelerators (RNGD) and a full stack hardware‑software platform to deliver energy‑efficient, high‑performance AI compute for enterprise and cloud customers.
Industry: Hardware Devices
Company Size: Medium (51 to 250 employees)
Growth: Scaleup
Valuation: USD 500M to 1B
Funding: Series C
Headquarters: Seoul, South Korea
Founded: 2017
Glassdoor
Glassdoor: 4.6
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