Memory Layout Design Engineer

Broadcom
India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsSkills: ["Communication","Leadership","Adaptability","Documentation","Collaboration"]

Design and verify high-quality memory layouts for advanced submicron FinFET processes (including TSMC 5nm/3nm/2nm and related nodes). Apply layout guidelines and new process rules, manage schedules and floor-planning, and ensure end-to-end deliverables are completed on time. Use Cadence and physical verification flows (Calibre, Hercules) for LVS/DRC/ERC and other checks, while collaborating with SOC and library teams and documenting methodologies.

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FursaFursa
Broadcom
Broadcom
4 days ago

Memory Layout Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Design and verify high-quality memory layouts for advanced submicron FinFET processes (including TSMC 5nm/3nm/2nm and related nodes). Apply layout guidelines and new process rules, manage schedules and floor-planning, and ensure end-to-end deliverables are completed on time. Use Cadence and physical verification flows (Calibre, Hercules) for LVS/DRC/ERC and other checks, while collaborating with SOC and library teams and documenting methodologies.
Location: India
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Apply layout guidelines, new process rules, and technical requirements to create high-quality memory layouts.
  • •Manage scheduling, timelines, and layout floor-planning, ensuring end-to-end deliverables meet quality and schedule targets.
  • •Perform and drive physical verification activities including LVS, DRC, ERC, Antenna, and Softcheck-related checks using Calibre and Hercules.
  • •Adapt quickly to new methodologies and communicate effectively with SOC and library teams.
  • •Lead technology reviews and document layout methodologies, flows, and guidelines; support training and knowledge transfer to junior engineers.

Key Requirements

  • •Minimum 8+ years of experience with a Bachelor's degree (or 6+ years with a Master's degree) and strong layout knowledge.
  • •Proficiency with Cadence tools including Virtuoso Layout, Layout XL, Cadence Schematic Capture, and verification tools Calibre and Hercules.
  • •Strong memory layout knowledge in advanced submicron FinFET processes, including TSMC 5nm, 3nm, 2nm, A14, or Samsung lower FinFET nodes.
  • •Experience with physical verification and checks including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
  • •Experience managing schedules/timelines and end-to-end deliverables for layout execution.
Experience:8+ yearsSemiconductorMemory layout
Skills:CommunicationLeadershipAdaptabilityDocumentationCollaboration
Tech Stack:CadenceVirtuoso LayoutLayout XLVXLEXLCadence Schematic CaptureCalibreHerculesLVSDRCERCAntennaElectro MigrationSoftcheckFloor-planningHierarchy layoutMemory compilersSKILLScript programmingTSMC 5nm

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn