ASIC Design Engineer, Clocks

NVIDIA
Shanghai
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 2+ yearsEducation: bachelorsSkills: ["Analytical thinking","Problem-solving","Communication","Teamwork","Ability to thrive in changing environments"]

Design and validate GPU clocking RTL for NVIDIA chips, collaborating with frontend and backend teams to meet architectural constraints. Work with architects, ASIC designers, and verification engineers to create high-frequency, low-power clocks, enhancing in-house flows to ensure RTL and netlist quality and driving issues to closure. Deliver clock information to SOC verification, timing, and DFT teams, using Perl/Python to improve productivity and debugging clock silicon bugs with software and silicon solution teams.

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FursaFursa
NVIDIA
NVIDIA
4 days ago

ASIC Design Engineer, Clocks

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Source: Company careers pageValidated by: Fursa AI
Last checked: 21 hours agoStatus: Live

Job Summary

Design and validate GPU clocking RTL for NVIDIA chips, collaborating with frontend and backend teams to meet architectural constraints. Work with architects, ASIC designers, and verification engineers to create high-frequency, low-power clocks, enhancing in-house flows to ensure RTL and netlist quality and driving issues to closure. Deliver clock information to SOC verification, timing, and DFT teams, using Perl/Python to improve productivity and debugging clock silicon bugs with software and silicon solution teams.
Location: Shanghai
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Collaborate with architects, ASIC designers, and verification engineers to design high-frequency, low-power GPU clocks.
  • •Engage with multiple teams to satisfy architectural constraints for GPU clocking designs.
  • •Run and enhance in-house flows to ensure RTL and netlist quality, driving issues to closure.
  • •Deliver clock information to SOC verification, timing, and DFT teams to support downstream development.
  • •Use Perl/Python to improve productivity and collaborate with software and silicon solution teams to debug GPU clock silicon bugs.

Key Requirements

  • •BS in EE (MS preferred) or equivalent experience, with 2+ years of meaningful work experience.
  • •Validated experience in RTL design using Verilog, verification, and logic synthesis.
  • •Strong coding skills in Perl or Python (or other industry-standard scripting languages) to improve engineering productivity.
  • •Deep understanding of sub-micron silicon issues such as noise, cross-talk, and OCV effects; backend flow knowledge is a plus.
  • •DFT knowledge is a plus, including experience implementing on-chip clocking networks; excellent analytical/problem-solving and communication skills with fluent English.
Experience:2+ yearsASICSemiconductorGPU
Education:Bachelor's in EE
Skills:Analytical thinkingProblem-solvingCommunicationTeamworkAbility to thrive in changing environments
Languages:English
Tech Stack:ASIC designGPU clockingRTLVerilogPerlPythonLogic synthesisNetlistSOC verificationTimingDFTOn-chip clocking networks

Company Brief

NVIDIA
Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1993
Glassdoor
Glassdoor: 4.3
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